51 lines
1.1 KiB
Scala
51 lines
1.1 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.core.Wire
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import chisel3.util.{ BitPat, Cat }
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/**
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* Don't touch these
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*/
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class SetupSignals extends Bundle {
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val IMEMsignals = new IMEMsetupSignals
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val DMEMsignals = new DMEMsetupSignals
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val registerSignals = new RegisterSetupSignals
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}
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class IMEMsetupSignals extends Bundle {
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val setup = Bool()
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val address = UInt(32.W)
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val instruction = UInt(32.W)
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}
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class DMEMsetupSignals extends Bundle {
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val setup = Bool()
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val writeEnable = Bool()
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val dataIn = UInt(32.W)
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val dataAddress = UInt(32.W)
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}
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class RegisterSetupSignals extends Bundle {
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val setup = Bool()
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val readAddress = UInt(5.W)
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val writeEnable = Bool()
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val writeAddress = UInt(5.W)
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val writeData = UInt(32.W)
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}
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class TestReadouts extends Bundle {
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val registerRead = UInt(32.W)
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val DMEMread = UInt(32.W)
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}
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class RegisterUpdates extends Bundle {
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val writeEnable = Bool()
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val writeData = UInt(32.W)
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val writeAddress = UInt(5.W)
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}
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class MemUpdates extends Bundle {
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val writeEnable = Bool()
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val writeData = UInt(32.W)
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val writeAddress = UInt(32.W)
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}
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