75 lines
2.5 KiB
Scala
75 lines
2.5 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.util._
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import chisel3.core.Input
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import chisel3.iotesters.PeekPokeTester
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/**
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* The top level module. You do not have to change anything here,
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* however you are free to route out signals as you see fit for debugging.
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*/
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class Tile() extends Module{
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val io = IO(
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new Bundle {
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val DMEMWriteData = Input(UInt(32.W))
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val DMEMAddress = Input(UInt(32.W))
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val DMEMWriteEnable = Input(Bool())
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val DMEMReadData = Output(UInt(32.W))
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val regsWriteData = Input(UInt(32.W))
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val regsAddress = Input(UInt(5.W))
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val regsWriteEnable = Input(Bool())
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val regsReadData = Output(UInt(32.W))
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val regsDeviceWriteEnable = Output(Bool())
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val regsDeviceWriteData = Output(UInt(32.W))
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val regsDeviceWriteAddress = Output(UInt(5.W))
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val memDeviceWriteEnable = Output(Bool())
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val memDeviceWriteData = Output(UInt(32.W))
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val memDeviceWriteAddress = Output(UInt(32.W))
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val IMEMWriteData = Input(UInt(32.W))
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val IMEMAddress = Input(UInt(32.W))
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val setup = Input(Bool())
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val currentPC = Output(UInt())
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})
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val CPU = Module(new CPU).testHarness
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CPU.setupSignals.IMEMsignals.address := io.IMEMAddress
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CPU.setupSignals.IMEMsignals.instruction := io.IMEMWriteData
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CPU.setupSignals.IMEMsignals.setup := io.setup
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CPU.setupSignals.DMEMsignals.writeEnable := io.DMEMWriteEnable
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CPU.setupSignals.DMEMsignals.dataAddress := io.DMEMAddress
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CPU.setupSignals.DMEMsignals.dataIn := io.DMEMWriteData
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CPU.setupSignals.DMEMsignals.setup := io.setup
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CPU.setupSignals.registerSignals.readAddress := io.regsAddress
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CPU.setupSignals.registerSignals.writeEnable := io.regsWriteEnable
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CPU.setupSignals.registerSignals.writeAddress := io.regsAddress
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CPU.setupSignals.registerSignals.writeData := io.regsWriteData
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CPU.setupSignals.registerSignals.setup := io.setup
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io.DMEMReadData := CPU.testReadouts.DMEMread
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io.regsReadData := CPU.testReadouts.registerRead
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io.regsDeviceWriteAddress := CPU.regUpdates.writeAddress
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io.regsDeviceWriteEnable := CPU.regUpdates.writeEnable
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io.regsDeviceWriteData := CPU.regUpdates.writeData
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io.memDeviceWriteAddress := CPU.memUpdates.writeAddress
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io.memDeviceWriteEnable := CPU.memUpdates.writeEnable
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io.memDeviceWriteData := CPU.memUpdates.writeData
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io.currentPC := CPU.currentPC
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}
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