57 lines
1.6 KiB
Scala
57 lines
1.6 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.core.Input
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import chisel3.experimental.MultiIOModule
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import chisel3.experimental._
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class CPU extends MultiIOModule {
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val testHarness = IO(
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new Bundle {
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val setupSignals = Input(new SetupSignals)
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val testReadouts = Output(new TestReadouts)
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val regUpdates = Output(new RegisterUpdates)
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val memUpdates = Output(new MemUpdates)
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val currentPC = Output(UInt(32.W))
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}
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)
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/**
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You need to create the classes for these yourself
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*/
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// val IFBarrier = Module(new IFBarrier).io
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// val IDBarrier = Module(new IDBarrier).io
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// val EXBarrier = Module(new EXBarrier).io
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// val MEMBarrier = Module(new MEMBarrier).io
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val ID = Module(new InstructionDecode)
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val IF = Module(new InstructionFetch)
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// val EX = Module(new Execute)
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val MEM = Module(new MemoryFetch)
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// val WB = Module(new Execute) (You may not need this one?)
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/**
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* Setup. You should not change this code
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*/
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IF.testHarness.IMEMsetup := testHarness.setupSignals.IMEMsignals
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ID.testHarness.registerSetup := testHarness.setupSignals.registerSignals
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MEM.testHarness.DMEMsetup := testHarness.setupSignals.DMEMsignals
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testHarness.testReadouts.registerRead := ID.testHarness.registerPeek
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testHarness.testReadouts.DMEMread := MEM.testHarness.DMEMpeek
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/**
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spying stuff
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*/
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testHarness.regUpdates := ID.testHarness.testUpdates
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testHarness.memUpdates := MEM.testHarness.testUpdates
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testHarness.currentPC := IF.testHarness.PC
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/**
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TODO: Your code here
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*/
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}
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