54 lines
1.3 KiB
Scala
54 lines
1.3 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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/**
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* This module is already done. Have one on me
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*/
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class DMEM extends MultiIOModule {
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// Don't touch the test harness
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val testHarness = IO(
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new Bundle {
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val setup = Input(new DMEMsetupSignals)
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val testUpdates = Output(new MemUpdates)
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})
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val io = IO(
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new Bundle {
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val writeEnable = Input(Bool())
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val dataIn = Input(UInt(32.W))
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val dataAddress = Input(UInt(12.W))
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val dataOut = Output(UInt(32.W))
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})
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val data = SyncReadMem(4096, UInt(32.W))
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val addressSource = Wire(UInt(32.W))
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val dataSource = Wire(UInt(32.W))
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val writeEnableSource = Wire(Bool())
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// For loading data
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when(testHarness.setup.setup){
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addressSource := testHarness.setup.dataAddress
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dataSource := testHarness.setup.dataIn
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writeEnableSource := testHarness.setup.writeEnable
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}.otherwise {
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addressSource := io.dataAddress
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dataSource := io.dataIn
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writeEnableSource := io.writeEnable
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}
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testHarness.testUpdates.writeEnable := writeEnableSource
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testHarness.testUpdates.writeData := dataSource
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testHarness.testUpdates.writeAddress := addressSource
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io.dataOut := data(addressSource)
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when(writeEnableSource){
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data(addressSource) := dataSource
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}
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}
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