package FiveStage import chisel3._ import chisel3.experimental.MultiIOModule class IDBarrier extends MultiIOModule { val io = IO( new Bundle { val op1in = Input(SInt(32.W)) val op1out = Output(SInt(32.W)) val isOp1RValueIn = Input(Bool()) val isOp1RValueOut = Output(Bool()) val op2in = Input(SInt(32.W)) val op2out = Output(SInt(32.W)) val isOp2RValueIn = Input(Bool()) val isOp2RValueOut = Output(Bool()) val r1ValueIn = Input(UInt(32.W)) val r1ValueOut = Output(UInt(32.W)) val r1AddressIn = Input(UInt(5.W)) val r1AddressOut = Output(UInt(5.W)) val r2ValueIn = Input(UInt(32.W)) val r2ValueOut = Output(UInt(32.W)) val r2AddressIn = Input(UInt(5.W)) val r2AddressOut = Output(UInt(5.W)) val returnAddrIn = Input(UInt(32.W)) val returnAddrOut = Output(UInt(32.W)) val jumpIn = Input(Bool()) val jumpOut = Output(Bool()) val ALUopIn = Input(UInt(4.W)) val ALUopOut = Output(UInt(4.W)) val branchTypeIn = Input(UInt(3.W)) val branchTypeOut = Output(UInt(3.W)) val writeAddrIn = Input(UInt(5.W)) val writeAddrOut = Output(UInt(5.W)) val writeEnableIn = Input(Bool()) val writeEnableOut = Output(Bool()) val memReadIn = Input(Bool()) val memReadOut = Output(Bool()) val memWriteIn = Input(Bool()) val memWriteOut = Output(Bool()) }) val isOp1RValue = RegInit(Bool(), false.B) isOp1RValue := io.isOp1RValueIn io.isOp1RValueOut := isOp1RValue val isOp2RValue = RegInit(Bool(), false.B) isOp2RValue := io.isOp2RValueIn io.isOp2RValueOut := isOp2RValue val r2Address = RegInit(UInt(5.W), 0.U) r2Address := io.r2AddressIn io.r2AddressOut := r2Address val r1Address = RegInit(UInt(5.W), 0.U) r1Address := io.r1AddressIn io.r1AddressOut := r1Address val op1 = RegInit(SInt(32.W), 0.S) op1 := io.op1in io.op1out := op1 val op2 = RegInit(SInt(32.W), 0.S) op2 := io.op2in io.op2out := op2 val r1Value = RegInit(UInt(32.W), 0.U) r1Value := io.r1ValueIn io.r1ValueOut := r1Value val r2Value = RegInit(UInt(32.W), 0.U) r2Value := io.r2ValueIn io.r2ValueOut := r2Value val returnAddr = RegInit(UInt(32.W), 0.U) returnAddr := io.returnAddrIn io.returnAddrOut := returnAddr val jump = RegInit(UInt(32.W), 0.U) jump := io.jumpIn io.jumpOut := jump val ALUop = RegInit(UInt(4.W), 0.U) ALUop := io.ALUopIn io.ALUopOut := ALUop val branchType = RegInit(UInt(5.W), 0.U) branchType := io.branchTypeIn io.branchTypeOut := branchType val writeAddr = RegInit(UInt(5.W), 0.U) writeAddr := io.writeAddrIn io.writeAddrOut := writeAddr val writeEnable = RegInit(Bool(), false.B) writeEnable := io.writeEnableIn io.writeEnableOut := writeEnable val memRead = RegInit(Bool(), false.B) memRead := io.memReadIn io.memReadOut := memRead val memWrite = RegInit(Bool(), false.B) memWrite := io.memWriteIn io.memWriteOut := memWrite }