package FiveStage import chisel3._ import chisel3.experimental.MultiIOModule class EXBarrierIO extends Bundle { val ALUResult = UInt(32.W) val returnAddr = UInt(32.W) val r2Value = UInt(32.W) val writeAddr = UInt(5.W) val writeEnable = Bool() val memRead = Bool() val memWrite = Bool() val branch = Bool() val jump = Bool() } class EXBarrier extends MultiIOModule { val io = IO( new Bundle { val in = Input(new EXBarrierIO) val out = Output(new EXBarrierIO) }) val delay = Reg(new EXBarrierIO) delay := io.in io.out := delay }