Half-working load.

src/main/scala/MEM.scala

@@ -18,6 +18,11 @@ class MemoryFetch() extends MultiIOModule {
 
   val io = IO(
     new Bundle {
+      val ALUResult = Input(UInt(32.W)) // We get ALUResult one cycle early
+      val writeData = Input(UInt(32.W))
+      val readMem = Input(Bool())
+      val writeMem = Input(Bool())
+      val dataOut = Output(UInt(32.W))
     })
 
 
@@ -35,7 +40,15 @@ class MemoryFetch() extends MultiIOModule {
   /**
     * Your code here.
     */
-  DMEM.io.dataIn      := 0.U
-  DMEM.io.dataAddress := 0.U
-  DMEM.io.writeEnable := false.B
+  DMEM.io.dataIn      := io.writeData
+  DMEM.io.dataAddress := io.ALUResult
+  DMEM.io.writeEnable := io.writeMem
+
+  // ALUResult is one cycle early!
+  val ALUResult = RegInit(UInt(32.W), 0.U)
+  ALUResult := io.ALUResult
+
+  when(io.readMem) {
+    io.dataOut := DMEM.io.dataOut
+  }.otherwise(io.dataOut := ALUResult)
 }