Half-working load.

src/main/scala/IDBarrier.scala

@@ -10,12 +10,18 @@ class IDBarrier extends MultiIOModule {
       val op1out = Output(SInt(32.W))
       val op2in = Input(SInt(32.W))
       val op2out = Output(SInt(32.W))
+      val r2ValueIn = Input(UInt(32.W))
+      val r2ValueOut = Output(UInt(32.W))
       val ALUopIn = Input(UInt(4.W))
       val ALUopOut = Output(UInt(4.W))
       val writeAddrIn = Input(UInt(5.W))
       val writeAddrOut = Output(UInt(5.W))
       val writeEnableIn = Input(Bool())
       val writeEnableOut = Output(Bool())
+      val memReadIn = Input(Bool())
+      val memReadOut = Output(Bool())
+      val memWriteIn = Input(Bool())
+      val memWriteOut = Output(Bool())
     })
 
   val op1 = RegInit(SInt(32.W), 0.S)
@@ -26,6 +32,10 @@ class IDBarrier extends MultiIOModule {
   op2 := io.op2in
   io.op2out := op2
 
+  val r2Value = RegInit(UInt(32.W), 0.U)
+  r2Value := io.r2ValueIn
+  io.r2ValueOut := r2Value
+
   val ALUop = RegInit(UInt(4.W), 0.U)
   ALUop := io.ALUopIn
   io.ALUopOut := ALUop
@@ -37,4 +47,12 @@ class IDBarrier extends MultiIOModule {
   val writeEnable = RegInit(Bool(), false.B)
   writeEnable := io.writeEnableIn
   io.writeEnableOut := writeEnable
+
+  val memRead = RegInit(Bool(), false.B)
+  memRead := io.memReadIn
+  io.memReadOut := memRead
+
+  val memWrite = RegInit(Bool(), false.B)
+  memWrite := io.memWriteIn
+  io.memWriteOut := memWrite
 }