Half-working load.

src/main/scala/ID.scala

@@ -22,12 +22,15 @@ class InstructionDecode extends MultiIOModule {
       val pc = Input(UInt(32.W))
       val op1 = Output(SInt(32.W))
       val op2 = Output(SInt(32.W))
+      val r2Value = Output(UInt(32.W))
       val ALUOp = Output(UInt(4.W))
       val writeAddrIn = Input(UInt(5.W))
       val writeAddrOut = Output(UInt(5.W))
       val writeEnableIn = Input(Bool())
       val writeEnableOut = Output(Bool())
       val writeData = Input(UInt(32.W))
+      val memWrite = Output(Bool())
+      val memRead = Output(Bool())
     }
   )
 
@@ -47,8 +50,9 @@ class InstructionDecode extends MultiIOModule {
   decoder.instruction := io.instruction
 
   val select1Map = Array(
-    Op1Select.rs1 -> registers.io.readData1.asSInt(),
-    Op1Select.PC -> io.pc.asSInt(),
+    Op1Select.rs1  -> registers.io.readData1.asSInt(),
+    Op1Select.PC   -> io.pc.asSInt(),
+    Op1Select.Zero -> 0.S
   )
   io.op1 := MuxLookup(decoder.op1Select, 0.S(32.W), select1Map)
 
@@ -65,8 +69,11 @@ class InstructionDecode extends MultiIOModule {
     Op2Select.rs2 -> registers.io.readData2.asSInt(),
   )
   io.op2 := MuxLookup(decoder.op2Select, 0.S(32.W), select2Map)
+  io.r2Value := registers.io.readData2
 
   io.ALUOp := decoder.ALUop
   io.writeAddrOut := decoder.instruction.registerRd
   io.writeEnableOut := decoder.controlSignals.regWrite
+  io.memRead := decoder.controlSignals.memRead
+  io.memWrite := decoder.controlSignals.memWrite
 }