Half-working load.

src/main/scala/EXBarrier.scala

@@ -6,17 +6,25 @@ import chisel3.experimental.MultiIOModule
 class EXBarrier extends MultiIOModule {
   val io = IO(
     new Bundle {
-      val writeDataIn = Input(UInt(32.W))
-      val writeDataOut = Output(UInt(32.W))
+      val ALUResultIn = Input(UInt(32.W))
+      val ALUResultOut = Output(UInt(32.W))
+      val r2ValueIn = Input(UInt(32.W))
+      val r2ValueOut = Output(UInt(32.W))
       val writeAddrIn = Input(UInt(5.W))
       val writeAddrOut = Output(UInt(5.W))
       val writeEnableIn = Input(Bool())
       val writeEnableOut = Output(Bool())
+      val memReadIn = Input(Bool())
+      val memReadOut = Output(Bool())
+      val memWriteIn = Input(Bool())
+      val memWriteOut = Output(Bool())
     })
 
-  val writeData = RegInit(UInt(32.W), 0.U)
-  writeData := io.writeDataIn
-  io.writeDataOut := writeData
+  io.ALUResultOut := io.ALUResultIn
+
+  val r2Value = RegInit(UInt(32.W), 0.U)
+  r2Value := io.r2ValueIn
+  io.r2ValueOut := r2Value
 
   val writeAddr = RegInit(UInt(5.W), 0.U)
   writeAddr := io.writeAddrIn
@@ -25,5 +33,13 @@ class EXBarrier extends MultiIOModule {
   val writeEnable = RegInit(Bool(), false.B)
   writeEnable := io.writeEnableIn
   io.writeEnableOut := writeEnable
+
+  val memRead = RegInit(Bool(), false.B)
+  memRead := io.memReadIn
+  io.memReadOut := memRead
+
+  val memWrite = RegInit(Bool(), false.B)
+  memWrite := io.memWriteIn
+  io.memWriteOut := memWrite
 }