Rewrite exercise stuff

src/main/scala/Const.scala

@@ -5,26 +5,6 @@ import chisel3.util._
 import chisel3.core.Input
 import chisel3.iotesters.PeekPokeTester
 
-
-// From RISC-V reference card
-object ALUOps {
-
-  val ADD    = 0.U(4.W)
-  val SUB    = 1.U(4.W)
-  val AND    = 2.U(4.W)
-  val OR     = 3.U(4.W)
-  val XOR    = 4.U(4.W)
-  val SLT    = 5.U(4.W)
-  val SLL    = 6.U(4.W)
-  val SLTU   = 7.U(4.W)
-  val SRL    = 8.U(4.W)
-  val SRA    = 9.U(4.W)
-  val COPY_A = 10.U(4.W)
-  val COPY_B = 11.U(4.W)
-
-  val DC     = 15.U(4.W)
-}
-
 object lookup {
   def BEQ                = BitPat("b?????????????????000?????1100011")
   def BNE                = BitPat("b?????????????????001?????1100011")

src/main/scala/Decoder.scala

@@ -40,7 +40,7 @@ class Decoder() extends Module {
     * The reason for this is that it serves as convenient sugar to make maps.
     * 
     * This doesn't matter to you, just fill in the blanks in the style currently
-    * used, I just want to demystify some of the magic.
+    * used, I just want to demystify some of the scala magic.
     * 
     * `a -> b` == `(a, b)` == `Tuple2(a, b)`
     */

src/main/scala/IF.scala

@@ -40,7 +40,7 @@ class InstructionFetch extends MultiIOModule {
   io.PC := PC
   IMEM.io.instructionAddress := PC
 
-  PC := PC + 4.U
+  // PC := PC + 4.U
 
   val instruction = Wire(new Instruction)
   instruction := IMEM.io.instruction.asTypeOf(new Instruction)

src/main/scala/ToplevelSignals.scala

@@ -103,3 +103,21 @@ object ImmFormat {
   val SHAMT  = 5.asUInt(3.W)
   val DC     = 0.asUInt(3.W)
 }
+
+
+object ALUOps {
+  val ADD    = 0.U(4.W)
+  val SUB    = 1.U(4.W)
+  val AND    = 2.U(4.W)
+  val OR     = 3.U(4.W)
+  val XOR    = 4.U(4.W)
+  val SLT    = 5.U(4.W)
+  val SLL    = 6.U(4.W)
+  val SLTU   = 7.U(4.W)
+  val SRL    = 8.U(4.W)
+  val SRA    = 9.U(4.W)
+  val COPY_A = 10.U(4.W)
+  val COPY_B = 11.U(4.W)
+
+  val DC     = 15.U(4.W)
+}