diff --git a/instructions.org b/instructions.org
index e323c7c..c4c9ea0 100644
--- a/instructions.org
+++ b/instructions.org
@@ -2,6 +2,8 @@
 4.2. Register-Register Arithmetic Instructions
 --------------------------------------------------------------------------
 
+These do not render well on github, try using your text editor.
+
 * ADD
 
  - Summary   : Addition with 3 GPRs, no overflow exception
diff --git a/src/test/scala/RISCV/printUtils.scala b/src/test/scala/RISCV/printUtils.scala
index f9d37b9..58adefa 100644
--- a/src/test/scala/RISCV/printUtils.scala
+++ b/src/test/scala/RISCV/printUtils.scala
@@ -347,7 +347,8 @@ object PrintUtils {
 
   def printLogSideBySide(trace: List[ExecutionTraceEvent], chiselTrace: List[CircuitTrace], program: Program): String = {
     import LogParser._
+    val header = "ADDRESS   --   VM UPDATES                                                ---      DEVICE UNDER TEST UPDATES                     ---    CORRESPONDING SOURCE LINE\n"
     val traces = mergeTraces(trace, chiselTrace).map(x => printMergedTraces((x), program))
-    traces.map(_.mkString("\n")).mkString("\n", "\n--------------------------------------------------------------------------+------------------------------------------------------+-------------------------------\n", "\n")
+    "\n" + header + (traces.map(_.mkString("\n")).mkString("\n", "\n--------------------------------------------------------------------------+------------------------------------------------------+-------------------------------\n", "\n"))
   }
 }