Working branching.

src/main/scala/ID.scala

@@ -39,7 +39,6 @@ class InstructionDecode extends MultiIOModule {
       val branchType = Output(UInt(3.W))
       val jump = Output(Bool())
       val returnAddr = Output(UInt(32.W))
-      val stall = Output(Bool())
     }
   )
 
@@ -88,25 +87,11 @@ class InstructionDecode extends MultiIOModule {
   io.ALUOp := decoder.ALUop
   io.writeAddrOut := decoder.instruction.registerRd
 
-  val stallsRemaining = RegInit(UInt(4.W), 0.U)
-  val stallDelay = stallsRemaining > 0.U
-  stallsRemaining := Mux(
-    stallDelay,
-    stallsRemaining - 1.U,
-    Mux(
-      decoder.controlSignals.branch,
-      3.U,
-      0.U
-    ))
-
-  val stall = stallsRemaining > 1.U || decoder.controlSignals.branch && !stallDelay
-  io.stall :=  stall
-
-  io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
-  io.branchType := Mux(stallDelay, branchType.DC, decoder.branchType)
+  io.jump := decoder.controlSignals.jump
+  io.branchType := decoder.branchType
   io.returnAddr := io.pc + 4.U
 
-  io.writeEnableOut := Mux(stallDelay, false.B, decoder.controlSignals.regWrite)
-  io.memRead := Mux(stallDelay, false.B, decoder.controlSignals.memRead)
-  io.memWrite := Mux(stallDelay, false.B, decoder.controlSignals.memWrite)
+  io.writeEnableOut := decoder.controlSignals.regWrite
+  io.memRead := decoder.controlSignals.memRead
+  io.memWrite := decoder.controlSignals.memWrite
 }