Add ex2 text. Remove unused file.
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* Exercise 1
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* Exercise description
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The task in this exercise is to implement a 5-stage pipelined processor for
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the [[./instructions.org][RISCV32I instruction set]].
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at a time, whereas in exercise 2 your design will handle multiple instructions
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at a time.
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This is done by inserting 4 NOP instructions inbetween each source instruction,
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enabling us to use the same tests for both exercise 1 and 2.
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enabling us to use the same tests and harness for both exercise 1 and 2.
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Once you are done with exercise 1, you can up the difficulty by setting nopPad
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to false and start reading the [[exercise2.org][ex2 guide]].
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In the project skeleton files ([[./src/main/scala/][Found here]]) you can see that a lot of code has
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already been provided, which can make it difficult to get started.
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