Working forwarding (i think).

src/main/scala/IDBarrier.scala

@@ -8,12 +8,18 @@ class IDBarrier extends MultiIOModule {
     new Bundle {
       val op1in = Input(SInt(32.W))
       val op1out = Output(SInt(32.W))
+      val isOp1RValue = Input(Bool())
       val op2in = Input(SInt(32.W))
       val op2out = Output(SInt(32.W))
+      val isOp2RValue = Input(Bool())
       val r1ValueIn = Input(UInt(32.W))
       val r1ValueOut = Output(UInt(32.W))
+      val r1AddressIn = Input(UInt(5.W))
+      val r1AddressOut = Output(UInt(5.W))
       val r2ValueIn = Input(UInt(32.W))
       val r2ValueOut = Output(UInt(32.W))
+      val r2AddressIn = Input(UInt(5.W))
+      val r2AddressOut = Output(UInt(5.W))
       val returnAddrIn = Input(UInt(32.W))
       val returnAddrOut = Output(UInt(32.W))
       val jumpIn = Input(Bool())
@@ -30,24 +36,76 @@ class IDBarrier extends MultiIOModule {
       val memReadOut = Output(Bool())
       val memWriteIn = Input(Bool())
       val memWriteOut = Output(Bool())
+
+      val forwardEx = Input(Bool())
+      val forwardExAddr = Input(UInt(5.W))
+      val forwardExData = Input(UInt(32.W))
+      val forwardMem = Input(Bool())
+      val forwardMemAddr = Input(UInt(5.W))
+      val forwardMemData = Input(UInt(32.W))
     })
 
+  val isOp1RValue = RegInit(Bool(), false.B)
+  isOp1RValue := io.isOp1RValue
+  val isOp2RValue = RegInit(Bool(), false.B)
+  isOp2RValue := io.isOp2RValue
+
   val op1 = RegInit(SInt(32.W), 0.S)
-  op1 := io.op1in
+  op1 := Mux(
+    io.forwardEx && io.isOp1RValue && io.r1AddressIn === io.forwardExAddr,
+    io.forwardExData.asSInt(),
+    Mux(
+      io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
+      io.forwardMemData.asSInt(),
+      io.op1in.asSInt(),
+    ),
+  )
   io.op1out := op1
 
   val op2 = RegInit(SInt(32.W), 0.S)
-  op2 := io.op2in
+  op2 := Mux(
+    io.forwardEx && io.isOp2RValue && io.r2AddressIn === io.forwardExAddr,
+    io.forwardExData.asSInt(),
+    Mux(
+      io.forwardMem && io.isOp2RValue && io.r2AddressIn === io.forwardMemAddr,
+      io.forwardMemData.asSInt(),
+      io.op2in,
+    ),
+  )
   io.op2out := op2
 
   val r1Value = RegInit(UInt(32.W), 0.U)
-  r1Value := io.r1ValueIn
+  r1Value := Mux(
+    io.forwardEx && io.r1AddressIn === io.forwardExAddr,
+    io.forwardExData,
+    Mux(
+      io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
+      io.forwardMemData,
+      io.r1ValueIn,
+    ),
+  )
   io.r1ValueOut := r1Value
 
+  val r1Address = RegInit(UInt(5.W), 0.U)
+  r1Address :=  io.r1AddressIn
+  io.r1AddressOut := r1Address
+
   val r2Value = RegInit(UInt(32.W), 0.U)
-  r2Value := io.r2ValueIn
+  r2Value := Mux(
+    io.forwardEx && io.r2AddressIn === io.forwardExAddr,
+    io.forwardExData,
+    Mux(
+      io.forwardMem && io.r2AddressIn === io.forwardMemAddr,
+      io.forwardMemData,
+      io.r2ValueIn,
+    ),
+  )
   io.r2ValueOut := r2Value
 
+  val r2Address = RegInit(UInt(5.W), 0.U)
+  r2Address := io.r2AddressIn
+  io.r2AddressOut := r2Address
+
   val returnAddr = RegInit(UInt(32.W), 0.U)
   returnAddr := io.returnAddrIn
   io.returnAddrOut := returnAddr