Working forwarding (i think).

src/main/scala/ID.scala

@@ -21,9 +21,13 @@ class InstructionDecode extends MultiIOModule {
       val instruction = Input(new Instruction)
       val pc = Input(UInt(32.W))
       val op1 = Output(SInt(32.W))
+      val isOp1RValue = Output(Bool())
       val op2 = Output(SInt(32.W))
+      val isOp2RValue = Output(Bool())
       val r1Value = Output(UInt(32.W))
+      val r1Address = Output(UInt(5.W))
       val r2Value = Output(UInt(32.W))
+      val r2Address = Output(UInt(5.W))
       val ALUOp = Output(UInt(4.W))
       val writeAddrIn = Input(UInt(5.W))
       val writeAddrOut = Output(UInt(5.W))
@@ -72,8 +76,13 @@ class InstructionDecode extends MultiIOModule {
     Op2Select.rs2 -> registers.io.readData2.asSInt(),
   )
   io.op2 := MuxLookup(decoder.op2Select, 0.S(32.W), select2Map)
+
+  io.isOp1RValue := decoder.op1Select === Op1Select.rs1
   io.r1Value := registers.io.readData1
+  io.r1Address := registers.io.readAddress1
+  io.isOp2RValue := decoder.op2Select === Op2Select.rs2
   io.r2Value := registers.io.readData2
+  io.r2Address := registers.io.readAddress2
 
   io.jump := decoder.controlSignals.jump
   io.returnAddr := io.pc + 4.U