Add MEMbarrier.

src/main/scala/CPU.scala

@@ -24,7 +24,7 @@ class CPU extends MultiIOModule {
   val IFBarrier  = Module(new IFBarrier).io
   val IDBarrier  = Module(new IDBarrier).io
   val EXBarrier  = Module(new EXBarrier).io
-  // val MEMBarrier = Module(new MEMBarrier).io
+  val MEMBarrier = Module(new MEMBarrier).io
 
   val ID  = Module(new InstructionDecode)
   val IF  = Module(new InstructionFetch)
@@ -102,10 +102,15 @@ class CPU extends MultiIOModule {
   MEM.io.readMem := EXBarrier.memReadOut
   MEM.io.writeData := EXBarrier.r2ValueOut
 
+  MEMBarrier.memRead := EXBarrier.memReadOut
+  MEMBarrier.dataIn := MEM.io.dataOut
+  MEMBarrier.writeEnableIn := EXBarrier.writeEnableOut
+  MEMBarrier.writeAddrIn := EXBarrier.writeAddrOut
+
   // Write back
-  ID.io.writeData := MEM.io.dataOut
-  ID.io.writeEnableIn := EXBarrier.writeEnableOut
-  ID.io.writeAddrIn := EXBarrier.writeAddrOut
+  ID.io.writeData := MEMBarrier.dataOut
+  ID.io.writeEnableIn := MEMBarrier.writeEnableOut
+  ID.io.writeAddrIn := MEMBarrier.writeAddrOut
 
   // Branching
   IF.io.branch := EXBarrier.branchOut
@@ -116,9 +121,13 @@ class CPU extends MultiIOModule {
   IDBarrier.forwardEx := EXBarrier.forwardEx
   IDBarrier.forwardExAddr := EXBarrier.forwardExAddr
 
-  IDBarrier.forwardMemData := MEM.io.dataOut
-  IDBarrier.forwardMem := EXBarrier.writeEnableOut
-  IDBarrier.forwardMemAddr := EXBarrier.writeAddrOut
+  IDBarrier.forwardMemData := MEMBarrier.forwardMemData
+  IDBarrier.forwardMem := MEMBarrier.forwardMem
+  IDBarrier.forwardMemAddr := MEMBarrier.forwardMemAddr
+
+  IDBarrier.forwardWbData := MEMBarrier.forwardWbData
+  IDBarrier.forwardWb := MEMBarrier.forwardWb
+  IDBarrier.forwardWbAddr := MEMBarrier.forwardWbAddr
 
   // Stall
   IF.io.stall := ID.io.stall

src/main/scala/IDBarrier.scala

@@ -43,6 +43,9 @@ class IDBarrier extends MultiIOModule {
       val forwardMem = Input(Bool())
       val forwardMemAddr = Input(UInt(5.W))
       val forwardMemData = Input(UInt(32.W))
+      val forwardWb = Input(Bool())
+      val forwardWbAddr = Input(UInt(5.W))
+      val forwardWbData = Input(UInt(32.W))
     })
 
   val isOp1RValue = RegInit(Bool(), false.B)
@@ -57,8 +60,12 @@ class IDBarrier extends MultiIOModule {
     Mux(
       io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
       io.forwardMemData.asSInt(),
+      Mux(
+        io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
+        io.forwardWbData.asSInt(),
         io.op1in.asSInt(),
       ),
+    ),
   )
   io.op1out := op1
 
@@ -69,8 +76,12 @@ class IDBarrier extends MultiIOModule {
     Mux(
       io.forwardMem && io.isOp2RValue && io.r2AddressIn === io.forwardMemAddr,
       io.forwardMemData.asSInt(),
+      Mux(
+        io.forwardWb && io.isOp2RValue && io.r2AddressIn === io.forwardWbAddr,
+        io.forwardWbData.asSInt(),
         io.op2in,
       ),
+    ),
   )
   io.op2out := op2
 
@@ -81,8 +92,12 @@ class IDBarrier extends MultiIOModule {
     Mux(
       io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
       io.forwardMemData,
+      Mux(
+        io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
+        io.forwardWbData,
         io.r1ValueIn,
       ),
+    ),
   )
   io.r1ValueOut := r1Value
 
@@ -97,8 +112,12 @@ class IDBarrier extends MultiIOModule {
     Mux(
       io.forwardMem && io.r2AddressIn === io.forwardMemAddr,
       io.forwardMemData,
+      Mux(
+        io.forwardWb && io.r2AddressIn === io.forwardWbAddr,
+        io.forwardWbData,
         io.r2ValueIn,
       ),
+    ),
   )
   io.r2ValueOut := r2Value
 

src/main/scala/MEMBarrier.scala

@@ -0,0 +1,45 @@
+package FiveStage
+import chisel3._
+import chisel3.experimental.MultiIOModule
+
+class MEMBarrier extends MultiIOModule {
+  val io = IO(
+    new Bundle {
+      val dataIn = Input(UInt(32.W))
+      val dataOut = Output(UInt(32.W))
+      val writeAddrIn = Input(UInt(5.W))
+      val writeAddrOut = Output(UInt(5.W))
+      val writeEnableIn = Input(Bool())
+      val writeEnableOut = Output(Bool())
+      val memRead = Input(Bool())
+      val forwardMem = Output(Bool())
+      val forwardMemAddr = Output(UInt(5.W))
+      val forwardMemData = Output(UInt(32.W))
+      val forwardWb = Output(Bool())
+      val forwardWbAddr = Output(UInt(5.W))
+      val forwardWbData = Output(UInt(32.W))
+    })
+
+  val memRead = RegInit(Bool(), false.B)
+  memRead := io.memRead
+
+  val data = RegInit(UInt(32.W), 0.U)
+  data := io.dataIn
+  io.dataOut := data
+
+  val writeAddr = RegInit(UInt(5.W), 0.U)
+  writeAddr := io.writeAddrIn
+  io.writeAddrOut := writeAddr
+
+  val writeEnable = RegInit(Bool(), false.B)
+  writeEnable := io.writeEnableIn
+  io.writeEnableOut := writeEnable
+
+  io.forwardMem := io.writeEnableIn
+  io.forwardMemAddr := io.writeAddrIn
+  io.forwardMemData := io.dataIn
+
+  io.forwardWb := writeEnable
+  io.forwardWbAddr := writeAddr
+  io.forwardWbData := data
+}

src/test/resources/tests/load3.s

@@ -0,0 +1,13 @@
+main:
+	sw x1, 2(x1)
+	lw x1, 4(x1)
+	done
+#memset 0x0,  4
+#memset 0x4,  8
+#memset 0x8,  12
+#memset 0xc,  16
+#memset 0x10, 20
+#memset 0x14, 20
+#memset 0x18, 20
+#memset 0x1c, 20
+#memset 0x20, 20

src/test/scala/Manifest.scala

@@ -19,7 +19,7 @@ import LogParser._
 
 object Manifest {
 
-  val singleTest = "addi.s"
+  val singleTest = "forward2.s"
 
   val nopPadded = false