kaholaz/TDT4255
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Add MEMbarrier.

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This commit is contained in:
Sebastian Bugge 2024-11-01 00:02:37 +01:00
parent b25cd420e8
commit af2cc43540
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
5 changed files with 98 additions and 12 deletions
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27
src/main/scala/IDBarrier.scala
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@ -43,6 +43,9 @@ class IDBarrier extends MultiIOModule {
val forwardMem = Input(Bool())
val forwardMemAddr = Input(UInt(5.W))
val forwardMemData = Input(UInt(32.W))
val forwardWb = Input(Bool())
val forwardWbAddr = Input(UInt(5.W))
val forwardWbData = Input(UInt(32.W))
})
val isOp1RValue = RegInit(Bool(), false.B)
@ -57,7 +60,11 @@ class IDBarrier extends MultiIOModule {
Mux(
io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
io.forwardMemData.asSInt(),
io.op1in.asSInt(),
Mux(
io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
io.forwardWbData.asSInt(),
io.op1in.asSInt(),
),
),
)
io.op1out := op1
@ -69,7 +76,11 @@ class IDBarrier extends MultiIOModule {
Mux(
io.forwardMem && io.isOp2RValue && io.r2AddressIn === io.forwardMemAddr,
io.forwardMemData.asSInt(),
io.op2in,
Mux(
io.forwardWb && io.isOp2RValue && io.r2AddressIn === io.forwardWbAddr,
io.forwardWbData.asSInt(),
io.op2in,
),
),
)
io.op2out := op2
@ -81,7 +92,11 @@ class IDBarrier extends MultiIOModule {
Mux(
io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
io.forwardMemData,
io.r1ValueIn,
Mux(
io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
io.forwardWbData,
io.r1ValueIn,
),
),
)
io.r1ValueOut := r1Value
@ -97,7 +112,11 @@ class IDBarrier extends MultiIOModule {
Mux(
io.forwardMem && io.r2AddressIn === io.forwardMemAddr,
io.forwardMemData,
io.r2ValueIn,
Mux(
io.forwardWb && io.r2AddressIn === io.forwardWbAddr,
io.forwardWbData,
io.r2ValueIn,
),
),
)
io.r2ValueOut := r2Value