kaholaz/TDT4255
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Add MEMbarrier.

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This commit is contained in:
Sebastian Bugge 2024-11-01 00:02:37 +01:00
parent b25cd420e8
commit af2cc43540
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
5 changed files with 98 additions and 12 deletions
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23
src/main/scala/CPU.scala
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@ -24,7 +24,7 @@ class CPU extends MultiIOModule {
val IFBarrier = Module(new IFBarrier).io
val IDBarrier = Module(new IDBarrier).io
val EXBarrier = Module(new EXBarrier).io
// val MEMBarrier = Module(new MEMBarrier).io
val MEMBarrier = Module(new MEMBarrier).io
val ID = Module(new InstructionDecode)
val IF = Module(new InstructionFetch)
@ -102,10 +102,15 @@ class CPU extends MultiIOModule {
MEM.io.readMem := EXBarrier.memReadOut
MEM.io.writeData := EXBarrier.r2ValueOut
MEMBarrier.memRead := EXBarrier.memReadOut
MEMBarrier.dataIn := MEM.io.dataOut
MEMBarrier.writeEnableIn := EXBarrier.writeEnableOut
MEMBarrier.writeAddrIn := EXBarrier.writeAddrOut
// Write back
ID.io.writeData := MEM.io.dataOut
ID.io.writeEnableIn := EXBarrier.writeEnableOut
ID.io.writeAddrIn := EXBarrier.writeAddrOut
ID.io.writeData := MEMBarrier.dataOut
ID.io.writeEnableIn := MEMBarrier.writeEnableOut
ID.io.writeAddrIn := MEMBarrier.writeAddrOut
// Branching
IF.io.branch := EXBarrier.branchOut
@ -116,9 +121,13 @@ class CPU extends MultiIOModule {
IDBarrier.forwardEx := EXBarrier.forwardEx
IDBarrier.forwardExAddr := EXBarrier.forwardExAddr
IDBarrier.forwardMemData := MEM.io.dataOut
IDBarrier.forwardMem := EXBarrier.writeEnableOut
IDBarrier.forwardMemAddr := EXBarrier.writeAddrOut
IDBarrier.forwardMemData := MEMBarrier.forwardMemData
IDBarrier.forwardMem := MEMBarrier.forwardMem
IDBarrier.forwardMemAddr := MEMBarrier.forwardMemAddr
IDBarrier.forwardWbData := MEMBarrier.forwardWbData
IDBarrier.forwardWb := MEMBarrier.forwardWb
IDBarrier.forwardWbAddr := MEMBarrier.forwardWbAddr
// Stall
IF.io.stall := ID.io.stall