Working SLT

This commit is contained in:
Sebastian Bugge 2024-09-27 08:31:56 +02:00
parent 39a6c5f87e
commit a48c9a1ba8
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
2 changed files with 3 additions and 3 deletions

View file

@ -21,8 +21,8 @@ class Execute extends MultiIOModule {
ALUOps.AND -> (io.op1 & io.op2),
ALUOps.OR -> (io.op1 | io.op2),
ALUOps.XOR -> (io.op1 ^ io.op2),
ALUOps.SLT -> (io.op1 < io.op2).asSInt(),
ALUOps.SLTU -> (io.op1.asUInt() < io.op2.asUInt()).asSInt(),
ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S),
ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S),
ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),

View file

@ -19,7 +19,7 @@ import LogParser._
object Manifest {
val singleTest = "load2.s"
val singleTest = "arithImm.s"
val nopPadded = true