Working SLT
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2 changed files with 3 additions and 3 deletions
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@ -21,8 +21,8 @@ class Execute extends MultiIOModule {
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ALUOps.AND -> (io.op1 & io.op2),
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ALUOps.AND -> (io.op1 & io.op2),
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ALUOps.OR -> (io.op1 | io.op2),
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ALUOps.OR -> (io.op1 | io.op2),
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ALUOps.XOR -> (io.op1 ^ io.op2),
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ALUOps.XOR -> (io.op1 ^ io.op2),
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ALUOps.SLT -> (io.op1 < io.op2).asSInt(),
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ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S),
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ALUOps.SLTU -> (io.op1.asUInt() < io.op2.asUInt()).asSInt(),
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ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S),
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ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
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ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
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ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
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ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
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ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
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ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
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@ -19,7 +19,7 @@ import LogParser._
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object Manifest {
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object Manifest {
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val singleTest = "load2.s"
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val singleTest = "arithImm.s"
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val nopPadded = true
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val nopPadded = true
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