Stuff I forgot to commit.
This commit is contained in:
peteraa
parent
b8ae0092c1
commit
9f47433501
14 changed files with 517 additions and 249 deletions
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@ -1,4 +1,5 @@
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package FiveStage
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import org.scalatest.{Matchers, FlatSpec}
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import cats._
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import cats.implicits._
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@ -20,7 +21,7 @@ object Manifest {
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val singleTest = "forward2.s"
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val nopPadded = true
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val nopPadded = false
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val singleTestOptions = TestOptions(
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printIfSuccessful = true,
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@ -53,18 +54,15 @@ object Manifest {
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class ProfileBranching extends FlatSpec with Matchers {
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it should "profile some branches" in {
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TestRunner.profileBranching(
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Manifest.singleTestOptions.copy(testName = "branchProfiling.s", maxSteps = 50000)
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BranchProfiler.profileBranching(
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Manifest.singleTestOptions.copy(testName = "branchProfiling.s", maxSteps = 150000)
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) should be(true)
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}
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}
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class ProfileCache extends FlatSpec with Matchers {
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it should "profile a cache" in {
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say("Warning, this test takes forever to run! 2 minutes on my machine at least.")
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say("This happens due to the less than optimal way of storing the update log. Sorry I guess")
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say("You probably want to debug this with a smaller program")
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TestRunner.profileCache(
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CacheProfiler.profileCache(
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Manifest.singleTestOptions.copy(testName = "convolution.s", maxSteps = 150000)
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) should be(true)
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}
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@ -176,8 +176,16 @@ object Data {
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val bitsRight = 32 - slots.log2
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val leftShifted = i << bitsLeft
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val rightShifted = leftShifted >>> bitsRight
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// say(i)
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// say(rightShifted)
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rightShifted
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}
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// To get the entire word call with from = 31, to = 0
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def bits(from: Int, to: Int): Int = {
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val bitsLeft = 31 - from
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val bitsRight = bitsLeft + to
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val leftShifted = i << bitsLeft
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val rightShifted = leftShifted >>> bitsRight
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rightShifted
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}
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}
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147
src/test/scala/RISCV/branchProfiler.scala
Normal file
147
src/test/scala/RISCV/branchProfiler.scala
Normal file
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@ -0,0 +1,147 @@
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package FiveStage
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import org.scalatest.{Matchers, FlatSpec}
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import cats._
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import cats.implicits._
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import fileUtils._
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import chisel3.iotesters._
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import scala.collection.mutable.LinkedHashMap
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import fansi.Str
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import Ops._
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import Data._
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import VM._
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import PrintUtils._
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import LogParser._
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object BranchProfiler {
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def profileBranching(testOptions: TestOptions): Boolean = {
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val testResults = for {
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lines <- fileUtils.readTest(testOptions)
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program <- FiveStage.Parser.parseProgram(lines, testOptions)
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(binary, (trace, finalVM)) <- program.validate(testOptions.maxSteps).map(x => (x._1, x._2.run))
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} yield {
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sealed trait BranchEvent
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case class Taken(from: Int, to: Int) extends BranchEvent { override def toString = s"Taken ${from.hs}\t${to.hs}" }
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case class NotTaken(addr: Int) extends BranchEvent { override def toString = s"Not Taken ${addr.hs}" }
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val events: List[BranchEvent] = trace.flatMap(_.event).collect{
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case PcUpdateBranch(from, to) => Taken(from.value, to.value)
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case PcUpdateNoBranch(at) => NotTaken(at.value)
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}
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/**
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* This is a sample profiler for a rather unrealistic branch predictor which has an unlimited amount
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* of slots
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*/
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def OneBitInfiniteSlots(events: List[BranchEvent]): Int = {
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// Uncomment to take a look at the event log
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// say(events.mkString("\n","\n","\n"))
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// Helper inspects the next element of the event list. If the event is a mispredict the prediction table is updated
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// to reflect this.
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// As long as there are remaining events the helper calls itself recursively on the remainder
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def helper(events: List[BranchEvent], predictionTable: Map[Int, Boolean]): Int = {
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events match {
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// Scala syntax for matching a list with a head element of some type and a tail
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// `case h :: t =>`
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// means we want to match a list with at least a head and a tail (tail can be Nil, so we
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// essentially want to match a list with at least one element)
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// h is the first element of the list, t is the remainder (which can be Nil, aka empty)
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// `case Constructor(arg1, arg2) :: t => `
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// means we want to match a list whose first element is of type Constructor, giving us access to its internal
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// values.
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// `case Constructor(arg1, arg2) :: t => if(p(arg1, arg2))`
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// means we want to match a list whose first element is of type Constructor while satisfying some predicate p,
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// called an if guard.
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case Taken(from, to) :: t if( predictionTable(from)) => helper(t, predictionTable)
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case Taken(from, to) :: t if(!predictionTable(from)) => 1 + helper(t, predictionTable.updated(from, true))
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case NotTaken(addr) :: t if( predictionTable(addr)) => 1 + helper(t, predictionTable.updated(addr, false))
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case NotTaken(addr) :: t if(!predictionTable(addr)) => helper(t, predictionTable)
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case Nil => 0
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}
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}
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// Initially every possible branch is set to false since the initial state of the predictor is to assume branch not taken
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def initState = events.map{
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case Taken(from, addr) => (from, false)
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case NotTaken(addr) => (addr, false)
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}.toMap
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helper(events, initState)
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}
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def twoBitPredictor(events: List[BranchEvent], slots: Int): Int = {
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case class nBitPredictor(
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values : List[Int],
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predictionRules : List[Boolean],
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transitionRules : Int => Boolean => Int,
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){
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val slots = values.size
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def predict(pc: Int): Boolean = predictionRules(values(pc.getTag(slots)))
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def update(pc: Int, taken: Boolean): nBitPredictor = {
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val current = values(pc.getTag(slots))
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val next = copy(values = values.updated(pc.getTag(slots), transitionRules(current)(taken)))
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next
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}
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override def toString = values.map(x => x.binary(2)).mkString("[","][","]")
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}
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val initPredictor = nBitPredictor(
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List.fill(slots)(0),
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List(
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false,
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false,
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true,
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true,
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),
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r => r match {
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case 0 => taken => if(taken) 1 else 0
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case 1 => taken => if(taken) 2 else 0
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case 2 => taken => if(taken) 3 else 1
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case 3 => taken => if(taken) 3 else 2
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}
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)
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events.foldLeft((0, initPredictor)){ case(((acc, bp), event)) =>
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println()
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say(s"total misses: $acc")
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say(event)
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event match {
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case Taken(pc, _) => say(s"taken at tag: ${pc.getTag(slots)}")
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case NotTaken(pc) => say(s"not taken at tag: ${pc.getTag(slots)}")
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}
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say(bp)
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event match {
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case Taken(pc, _) if bp.predict(pc) => {say("HIT!"); (acc, bp.update(pc, true))}
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case Taken(pc, _) => {say("MISS!"); (acc + 1, bp.update(pc, true))}
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case NotTaken(pc) if !bp.predict(pc) => {say("HIT!"); (acc, bp.update(pc, false))}
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case NotTaken(pc) => {say("MISS!"); (acc + 1, bp.update(pc, false))}
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}
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}._1
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}
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say(events.mkString("\n","\n","\n"))
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say(twoBitPredictor(events, 8))
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}
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true
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}
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}
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204
src/test/scala/RISCV/cacheProfiler.scala
Normal file
204
src/test/scala/RISCV/cacheProfiler.scala
Normal file
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@ -0,0 +1,204 @@
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package FiveStage
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import org.scalatest.{Matchers, FlatSpec}
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import cats._
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import cats.implicits._
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import fileUtils._
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import chisel3.iotesters._
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import scala.collection.mutable.LinkedHashMap
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import fansi.Str
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import Ops._
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import Data._
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import VM._
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import PrintUtils._
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import LogParser._
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object CacheProfiler {
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def profileCache(testOptions: TestOptions): Boolean = {
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val testResults = for {
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lines <- fileUtils.readTest(testOptions)
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program <- FiveStage.Parser.parseProgram(lines, testOptions)
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(binary, (trace, finalVM)) <- program.validate(testOptions.maxSteps).map(x => (x._1, x._2.run))
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} yield {
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import TestUtils._
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sealed trait MemoryEvent
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case class Write(addr: Int) extends MemoryEvent
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case class Read(addr: Int) extends MemoryEvent
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val events = trace.flatMap(_.event).collect{
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case MemWrite(addr, _) => Write(addr.value)
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case MemRead(addr, _) => Read(addr.value)
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}
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class CacheProfiler(setCount: Int, setSize: Int, blockSize: Int){
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// If we set counter to 0 we risk evicting the first allocated block.
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var counter = 1
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var misses = 0
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var mostRecent = 0
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var wasMiss = false
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implicit class AddrOps(i: Int){
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val blockOffsetBits = blockSize.log2
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val lineBits = setSize.log2
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def lineIdx: Int = {
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i.bits(2 + blockOffsetBits + lineBits - 1, 2 + blockOffsetBits)
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}
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}
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case class CacheLine(tag: Int, lastUsed: Int){
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def matches(addr: Int): Boolean = List.fill(blockSize)(tag)
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.zipWithIndex
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.map{ case(btag, idx) => btag + idx*4 }
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.map(_ == addr)
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.foldLeft(false)(_ || _)
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def renderContent(addr: Int): String = (addr == mostRecent, wasMiss) match {
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case (true, true) => Console.RED + addr.hs + Console.RESET
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case (true, false) => Console.GREEN + addr.hs + Console.RESET
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case _ => addr.hs
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}
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def render: String = {
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val blockContents = List.fill(blockSize)(tag)
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.zipWithIndex
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.map{ case(btag, idx) => renderContent(btag + idx*4) }
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.mkString("Contents: || ", " | ", " |")
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s"Base: ${tag.hs} LRU: $lastUsed\t" + blockContents
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}
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}
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object CacheLine {
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def truncateTag(addr: Int) = addr - (addr % (blockSize*4))
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}
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case class CacheSet(blocks: Array[CacheLine]){
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def lineIdx(addr: Int): Int = addr.lineIdx
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def contains(addr: Int): Boolean = blocks.map(_.matches(addr)).foldLeft(false)(_ || _)
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def updateLRU(addr: Int): Unit = {
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val idx = lineIdx(addr)
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val next = blocks(idx).copy(lastUsed = counter)
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blocks(idx) = next
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}
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def render: String = {
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blocks.map(_.render).mkString("\n", "\n", "\n")
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}
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}
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case class Cache(sets: Array[CacheSet]){
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/** returns the index of set if hit */
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def checkHit(addr: Int): Option[Int] = sets
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.zipWithIndex
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.map{ case(set, idx) => Option.when(set.contains(addr))(idx) }
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.flatten.headOption
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/** Updates the LRU counter */
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def updateLRU(addr: Int, setIdx: Int): Unit = sets(setIdx).updateLRU(addr)
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/** Gets set with least recently used */
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def getLRU(addr: Int): Int = sets
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.map( set => set.blocks(set.lineIdx(addr)).lastUsed)
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.zipWithIndex
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.sortBy(_._1)
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.map(_._2)
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.head
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/** Entry point */
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def handleAccess(addr: Int): Unit = {
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mostRecent = addr
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counter += 1
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checkHit(addr) match {
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case Some(setIdx) => {
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wasMiss = false
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updateLRU(addr, setIdx)
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// say(s"${addr.hs} HIT")
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}
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case None => {
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val set = sets(getLRU(addr))
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val nextTag = CacheLine.truncateTag(addr)
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set.blocks(set.lineIdx(addr)) = set.blocks(set.lineIdx(addr)).copy(
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tag = nextTag,
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lastUsed = counter
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)
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misses += 1
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wasMiss = true
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// say(s"${addr.hs} MISS")
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// say(s"BLOCK ${addr.lineIdx} IN SET ${getLRU(addr)} EVICTED. BYE BYE")
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}
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}
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}
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/** Pretty pictures! */
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def render: String = {
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sets.map(_.render).mkString("\n", "\n", "\n")
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}
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}
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object Cache {
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def init: Cache = Cache(Array.fill(setCount)(
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CacheSet(Array.fill(setSize)(CacheLine(57005, 0))))
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)
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}
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}
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for{
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sets <- List(2, 4, 8)
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blockSize <- List(4, 8)
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lines <- List(2, 4, 8)
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} yield {
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val myTest = new CacheProfiler(sets, lines, blockSize)
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val myCache = myTest.Cache.init
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events.foreach{
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case Write(addr) => myCache.handleAccess(addr)
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case Read(addr) => myCache.handleAccess(addr)
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}
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say(s"sets: $sets, lines: $lines, blockSize: $blockSize yields ${myTest.misses} misses")
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}
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// val myTest = new CacheProfiler(2, 4, 4)
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// val myCache = myTest.Cache.init
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// events.foreach{
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// case Write(addr) => {
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// say(addr.hs)
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// myCache.handleAccess(addr)
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// say(myCache.render)
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// }
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// case Read(addr) => {
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// say(addr.hs)
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// myCache.handleAccess(addr)
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// say(myCache.render)
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// }
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// }
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// say(myTest.misses)
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}
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true
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}
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}
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@ -101,98 +101,4 @@ object TestRunner {
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successful
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}.toOption.getOrElse(false)
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}
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def profileBranching(testOptions: TestOptions): Boolean = {
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val testResults = for {
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lines <- fileUtils.readTest(testOptions)
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program <- FiveStage.Parser.parseProgram(lines, testOptions)
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(binary, (trace, finalVM)) <- program.validate(testOptions.maxSteps).map(x => (x._1, x._2.run))
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} yield {
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sealed trait BranchEvent
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case class Taken(from: Int, to: Int) extends BranchEvent { override def toString = s"Taken ${from.hs}\t${to.hs}" }
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case class NotTaken(addr: Int) extends BranchEvent { override def toString = s"Not Taken ${addr.hs}" }
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val events: List[BranchEvent] = trace.flatMap(_.event).collect{
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case PcUpdateBranch(from, to) => Taken(from.value, to.value)
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case PcUpdateNoBranch(at) => NotTaken(at.value)
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}
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|
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/**
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* This is a sample profiler for a rather unrealistic branch predictor which has an unlimited amount
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* of slots
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*/
|
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def OneBitInfiniteSlots(events: List[BranchEvent]): Int = {
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|
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// Uncomment to take a look at the event log
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// say(events.mkString("\n","\n","\n"))
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|
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// Helper inspects the next element of the event list. If the event is a mispredict the prediction table is updated
|
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// to reflect this.
|
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// As long as there are remaining events the helper calls itself recursively on the remainder
|
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def helper(events: List[BranchEvent], predictionTable: Map[Int, Boolean]): Int = {
|
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events match {
|
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|
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// Scala syntax for matching a list with a head element of some type and a tail
|
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// `case h :: t =>`
|
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// means we want to match a list with at least a head and a tail (tail can be Nil, so we
|
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// essentially want to match a list with at least one element)
|
||||
// h is the first element of the list, t is the remainder (which can be Nil, aka empty)
|
||||
|
||||
// `case Constructor(arg1, arg2) :: t => `
|
||||
// means we want to match a list whose first element is of type Constructor, giving us access to its internal
|
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// values.
|
||||
|
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// `case Constructor(arg1, arg2) :: t => if(p(arg1, arg2))`
|
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// means we want to match a list whose first element is of type Constructor while satisfying some predicate p,
|
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// called an if guard.
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case Taken(from, to) :: t if( predictionTable(from)) => helper(t, predictionTable)
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case Taken(from, to) :: t if(!predictionTable(from)) => 1 + helper(t, predictionTable.updated(from, true))
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case NotTaken(addr) :: t if( predictionTable(addr)) => 1 + helper(t, predictionTable.updated(addr, false))
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case NotTaken(addr) :: t if(!predictionTable(addr)) => helper(t, predictionTable)
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case Nil => 0
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}
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}
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|
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// Initially every possible branch is set to false since the initial state of the predictor is to assume branch not taken
|
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def initState = events.map{
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case Taken(from, addr) => (from, false)
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case NotTaken(addr) => (addr, false)
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||||
}.toMap
|
||||
|
||||
helper(events, initState)
|
||||
}
|
||||
|
||||
say(OneBitInfiniteSlots(events))
|
||||
}
|
||||
|
||||
|
||||
true
|
||||
}
|
||||
|
||||
|
||||
def profileCache(testOptions: TestOptions): Boolean = {
|
||||
|
||||
val testResults = for {
|
||||
lines <- fileUtils.readTest(testOptions)
|
||||
program <- FiveStage.Parser.parseProgram(lines, testOptions)
|
||||
(binary, (trace, finalVM)) <- program.validate(testOptions.maxSteps).map(x => (x._1, x._2.run))
|
||||
} yield {
|
||||
|
||||
sealed trait MemoryEvent
|
||||
case class Write(addr: Int) extends MemoryEvent
|
||||
case class Read(addr: Int) extends MemoryEvent
|
||||
|
||||
val events: List[MemoryEvent] = trace.flatMap(_.event).collect{
|
||||
case MemWrite(x,_) => Write(x.value)
|
||||
case MemRead(x,_) => Read(x.value)
|
||||
}
|
||||
|
||||
// Your cache here
|
||||
|
||||
}
|
||||
true
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,6 +6,10 @@ import PrintUtils._
|
|||
|
||||
object TestUtils {
|
||||
|
||||
implicit class OptionBackport(t: Option.type){
|
||||
def when[T](b: Boolean)(t: => T) = if(b) Some(t) else None
|
||||
}
|
||||
|
||||
/**
|
||||
* Generate and serialize BTrees for the test runner
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ private class ChiselTestRunner (
|
|||
|
||||
// After finishing, let the circuit run until all updates can be committed.
|
||||
private def flush: List[CircuitTrace] =
|
||||
(0 to 3).map(_ => stepOne).reverse.toList
|
||||
(0 to 4).map(_ => stepOne).reverse.toList
|
||||
|
||||
/**
|
||||
* Run the entire shebang
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue