Lower branch cycles to two.

src/main/scala/CPU.scala

@@ -106,7 +106,7 @@ class CPU extends MultiIOModule {
 
   EXBarrier.in.r2Value := EX.io.rs2ValueOut.asUInt()
   EXBarrier.in.ALUResult := EX.io.ALUResult.asUInt()
-  EXBarrier.in.branch := EX.io.branch
+  EXBarrier.branchIn := EX.io.branch
   EXBarrier.in.jump := IDBarrier.out.jump
   EXBarrier.in.returnAddr := IDBarrier.out.returnAddr
   EXBarrier.in.writeEnable := IDBarrier.out.writeEnable
@@ -132,8 +132,8 @@ class CPU extends MultiIOModule {
   ID.io.writeAddrIn := MEMBarrier.out.writeAddr
 
   // Branching
-  IF.io.branch := EXBarrier.out.branch
-  IF.io.branchAddress := EXBarrier.out.ALUResult
+  IF.io.branch := EXBarrier.branchOut
+  IF.io.branchAddress := EXBarrier.branchAddr
 
   // Stall
   IF.io.stall := IDBarrier.stall

src/main/scala/EXBarrier.scala

@@ -11,7 +11,6 @@ class EXBarrierIO extends Bundle {
   val writeEnable = Bool()
   val memRead = Bool()
   val memWrite = Bool()
-  val branch = Bool()
   val jump = Bool()
 }
 
@@ -21,11 +20,16 @@ class EXBarrier extends MultiIOModule {
       val in = Input(new EXBarrierIO)
       val out = Output(new EXBarrierIO)
       val flush = Output(Bool())
+      val branchAddr = Output(UInt(32.W))
+      val branchIn = Input(Bool())
+      val branchOut = Output(Bool())
     })
 
   val delay = Reg(new EXBarrierIO)
   delay := io.in
   io.out := delay
 
-  io.flush := io.in.branch
+  io.flush := io.branchIn
+  io.branchOut := io.branchIn
+  io.branchAddr := io.in.ALUResult
 }

src/main/scala/IFBarrier.scala

@@ -23,7 +23,7 @@ class IFBarrier extends MultiIOModule {
   val flushRemaining = RegInit(UInt(2.W), 0.U)
   flushRemaining := Mux(
     io.flush,
-    2.U,
+    1.U,
     Mux(
       flushRemaining === 0.U,
       0.U,