kaholaz/TDT4255
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Actually fix forwarding.

Browse source
This commit is contained in:
Sebastian Bugge 2024-11-01 03:02:36 +01:00
parent 4c684f1718
commit 97b13a813f
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
5 changed files with 78 additions and 79 deletions
Download patch file Download diff file Expand all files Collapse all files

124
src/main/scala/IDBarrier.scala
View file

@ -37,15 +37,15 @@ class IDBarrier extends MultiIOModule {
val memWriteIn = Input(Bool())
val memWriteOut = Output(Bool())
val forwardEx = Input(Bool())
val forwardExAddr = Input(UInt(5.W))
val forwardExData = Input(UInt(32.W))
val forwardMem = Input(Bool())
val forwardMemAddr = Input(UInt(5.W))
val forwardMemData = Input(UInt(32.W))
val forwardWb = Input(Bool())
val forwardWbAddr = Input(UInt(5.W))
val forwardWbData = Input(UInt(32.W))
val forwardId = Input(Bool())
val forwardIdAddr = Input(UInt(5.W))
val forwardIdData = Input(UInt(32.W))
})
val isOp1RValue = RegInit(Bool(), false.B)
@ -53,77 +53,69 @@ class IDBarrier extends MultiIOModule {
val isOp2RValue = RegInit(Bool(), false.B)
isOp2RValue := io.isOp2RValue
val op1 = RegInit(SInt(32.W), 0.S)
op1 := Mux(
io.forwardEx && io.isOp1RValue && io.r1AddressIn === io.forwardExAddr,
io.forwardExData.asSInt(),
Mux(
io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
io.forwardWbData.asSInt(),
io.op1in.asSInt(),
),
),
)
io.op1out := op1
val op2 = RegInit(SInt(32.W), 0.S)
op2 := Mux(
io.forwardEx && io.isOp2RValue && io.r2AddressIn === io.forwardExAddr,
io.forwardExData.asSInt(),
Mux(
io.forwardMem && io.isOp2RValue && io.r2AddressIn === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardWb && io.isOp2RValue && io.r2AddressIn === io.forwardWbAddr,
io.forwardWbData.asSInt(),
io.op2in,
),
),
)
io.op2out := op2
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := Mux(
io.forwardEx && io.r1AddressIn === io.forwardExAddr,
io.forwardExData,
Mux(
io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
io.forwardMemData,
Mux(
io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
io.forwardWbData,
io.r1ValueIn,
),
),
)
io.r1ValueOut := r1Value
val r2Address = RegInit(UInt(5.W), 0.U)
r2Address := io.r2AddressIn
io.r2AddressOut := r2Address
val r1Address = RegInit(UInt(5.W), 0.U)
r1Address := io.r1AddressIn
io.r1AddressOut := r1Address
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := Mux(
io.forwardEx && io.r2AddressIn === io.forwardExAddr,
io.forwardExData,
val op1 = RegInit(SInt(32.W), 0.S)
op1 := io.op1in
io.op1out := Mux(
io.forwardMem && isOp1RValue && r1Address === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardMem && io.r2AddressIn === io.forwardMemAddr,
io.forwardMemData,
io.forwardWb && isOp1RValue && r1Address === io.forwardWbAddr,
io.forwardWbData.asSInt(),
Mux(
io.forwardWb && io.r2AddressIn === io.forwardWbAddr,
io.forwardWbData,
io.r2ValueIn,
),
),
)
io.r2ValueOut := r2Value
io.forwardId && isOp1RValue && r1Address === io.forwardIdAddr,
io.forwardIdData.asSInt(),
op1.asSInt(),
)))
val r2Address = RegInit(UInt(5.W), 0.U)
r2Address := io.r2AddressIn
io.r2AddressOut := r2Address
val op2 = RegInit(SInt(32.W), 0.S)
op2 := io.op2in
io.op2out := Mux(
io.forwardMem && isOp2RValue && r2Address === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardWb && isOp2RValue && r2Address === io.forwardWbAddr,
io.forwardWbData.asSInt(),
Mux(
io.forwardId && isOp2RValue && r2Address === io.forwardIdAddr,
io.forwardIdData.asSInt(),
op2.asSInt(),
)))
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := io.r1ValueIn
io.r1ValueOut := Mux(
io.forwardMem && r1Address === io.forwardMemAddr,
io.forwardMemData,
Mux(
io.forwardWb && r1Address === io.forwardWbAddr,
io.forwardWbData,
Mux(
io.forwardId && r1Address === io.forwardIdAddr,
io.forwardIdData,
r1Value,
)))
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := io.r2ValueIn
io.r2ValueOut := Mux(
io.forwardMem && r2Address === io.forwardMemAddr,
io.forwardMemData,
Mux(
io.forwardWb && r2Address === io.forwardWbAddr,
io.forwardWbData,
Mux(
io.forwardId && r2Address === io.forwardIdAddr,
io.forwardIdData,
r2Value,
)))
val returnAddr = RegInit(UInt(32.W), 0.U)
returnAddr := io.returnAddrIn