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Add working 4real.

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Sebastian Bugge 2024-09-27 04:47:26 +02:00
parent 44ccf12cad
commit 961ae49523
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
4 changed files with 29 additions and 23 deletions
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38
src/main/scala/Decoder.scala
View file

@ -47,26 +47,26 @@ class Decoder() extends Module {
val opcodeMap: Array[(BitPat, List[UInt])] = Array(
// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD ),
SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB ),
AND -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.AND ),
OR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.OR ),
XOR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.XOR ),
SLT -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLT ),
SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU),
SRA -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRA ),
SRL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRL ),
SLL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLL ),
ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD ),
SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB ),
AND -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.AND ),
OR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.OR ),
XOR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.XOR ),
SLT -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLT ),
SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU),
SRA -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRA ),
SRL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRL ),
SLL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLL ),
ADDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ),
ANDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.AND ),
ORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.OR ),
XORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.XOR ),
SLTI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLT ),
SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU),
SRAI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.SHORT_ITYPE, ALUOps.SRA ),
SRLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.SHORT_ITYPE, ALUOps.SRL ),
SLLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.SHORT_ITYPE, ALUOps.SLL ),
ADDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ),
ANDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.AND ),
ORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.OR ),
XORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.XOR ),
SLTI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLT ),
SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU),
SRAI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRA ),
SRLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRL ),
SLLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLL ),
)

11
src/main/scala/EX.scala
View file

@ -16,7 +16,16 @@ class Execute extends MultiIOModule {
)
val ALUOpsMap = Array (
ALUOps.ADD -> (io.op1 + io.op2)
ALUOps.ADD -> (io.op1 + io.op2),
ALUOps.SUB -> (io.op1 - io.op2),
ALUOps.AND -> (io.op1 & io.op2),
ALUOps.OR -> (io.op1 | io.op2),
ALUOps.XOR -> (io.op1 ^ io.op2),
ALUOps.SLT -> (io.op1 < io.op2).asSInt(),
ALUOps.SLTU -> (io.op1.asUInt() < io.op2.asUInt()).asSInt(),
ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
)
io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap)

1
src/main/scala/ID.scala
View file

@ -59,7 +59,6 @@ class InstructionDecode extends MultiIOModule {
ImmFormat.UTYPE -> decoder.instruction.immediateUType,
ImmFormat.JTYPE -> decoder.instruction.immediateJType,
ImmFormat.SHAMT -> decoder.instruction.immediateZType,
ImmFormat.SHORT_ITYPE -> decoder.instruction.immediateShortIType,
)
val select2Map = Array(
Op2Select.imm -> MuxLookup(decoder.immType, 0.S(32.W), select2ImmMap),

2
src/main/scala/ToplevelSignals.scala
View file

@ -21,7 +21,6 @@ class Instruction extends Bundle(){
def immediateUType = Cat(instruction(31, 12), 0.U(12.W)).asSInt
def immediateJType = Cat(instruction(31), instruction(19, 12), instruction(20), instruction(30, 25), instruction(24, 21), 0.U(1.W)).asSInt
def immediateZType = instruction(19, 15).zext
def immediateShortIType = instruction(24, 20).asSInt
def bubble(): Instruction = {
val bubbled = Wire(new Instruction)
@ -103,7 +102,6 @@ object ImmFormat {
val UTYPE = 3.asUInt(3.W)
val JTYPE = 4.asUInt(3.W)
val SHAMT = 5.asUInt(3.W)
val SHORT_ITYPE = 6.asUInt(3.W)
val DC = 0.asUInt(3.W)
}