This commit is contained in:
peteraa 2019-06-07 17:43:33 +02:00
commit 932413bb3d
61 changed files with 7249 additions and 0 deletions

41
src/main/scala/MEM.scala Normal file
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package FiveStage
import chisel3._
import chisel3.util._
import chisel3.experimental.MultiIOModule
class MemoryFetch() extends MultiIOModule {
// Don't touch the test harness
val testHarness = IO(
new Bundle {
val DMEMsetup = Input(new DMEMsetupSignals)
val DMEMpeek = Output(UInt(32.W))
val testUpdates = Output(new MemUpdates)
})
val io = IO(
new Bundle {
})
val DMEM = Module(new DMEM)
/**
* Setup. You should not change this code
*/
DMEM.testHarness.setup := testHarness.DMEMsetup
testHarness.DMEMpeek := DMEM.io.dataOut
testHarness.testUpdates := DMEM.testHarness.testUpdates
/**
* Your code here.
*/
DMEM.io.dataIn := 0.U
DMEM.io.dataAddress := 0.U
DMEM.io.writeEnable := false.B
}