Nuke

src/main/scala/Decoder.scala

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+package FiveStage
+import chisel3._
+import chisel3.util.BitPat
+import chisel3.util.ListLookup
+
+
+/**
+  * This module is mostly done, but you will have to fill in the blanks in opcodeMap.
+  * You may want to add more signals to be decoded in this module depending on your
+  * design if you so desire.
+  * 
+  * In the "classic" 5 stage decoder signals such as op1select and immType
+  * are not included, however I have added them to my design, and similarily you might
+  * find it useful to add more
+ */
+class Decoder() extends Module {
+
+  val io = IO(new Bundle {
+                val instruction    = Input(new Instruction)
+
+                val controlSignals = Output(new ControlSignals)
+                val branchType     = Output(UInt(3.W))
+                val op1Select      = Output(UInt(1.W))
+                val op2Select      = Output(UInt(1.W))
+                val immType        = Output(UInt(3.W))
+                val ALUop          = Output(UInt(4.W))
+              })
+
+  import lookup._
+  import Op1Select._
+  import Op2Select._
+  import branchType._
+  import ImmFormat._
+
+  val N = 0.asUInt(1.W)
+  val Y = 1.asUInt(1.W)
+
+  /**
+    * In scala we sometimes (ab)use the `->` operator to create tuples. 
+    * The reason for this is that it serves as convenient sugar to make maps.
+    * 
+    * This doesn't matter to you, just fill in the blanks in the style currently
+    * used, I just want to demystify some of the magic.
+    * 
+    * `a -> b` == `(a, b)` == `Tuple2(a, b)`
+    */
+  val opcodeMap: Array[(BitPat, List[UInt])] = Array(
+
+    // signal      memToReg, regWrite, memRead, memWrite, branch,  jump, branchType,    Op1Select, Op2Select, ImmSelect,    ALUOp
+    LW     -> List(Y,        Y,        Y,       N,        N,       N,    branchType.DC, rs1,       imm,       ITYPE,        ALUOps.ADD),
+
+    SW     -> List(N,        N,        N,       Y,        N,       N,    branchType.DC, rs1,       imm,       STYPE,        ALUOps.ADD),
+
+    ADD    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.ADD),
+    SUB    -> List(N,        Y,        N,       N,        N,       N,    branchType.DC, rs1,       rs2,       ImmFormat.DC, ALUOps.SUB),
+
+    /**
+      TODO: Fill in the blanks
+      */
+    )
+
+
+  val NOP = List(N, N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
+
+  val decodedControlSignals = ListLookup(
+    io.instruction.asUInt(),
+    NOP,
+    opcodeMap)
+
+  io.controlSignals.memToReg   := decodedControlSignals(0)
+  io.controlSignals.regWrite   := decodedControlSignals(1)
+  io.controlSignals.memRead    := decodedControlSignals(2)
+  io.controlSignals.memWrite   := decodedControlSignals(3)
+  io.controlSignals.branch     := decodedControlSignals(4)
+  io.controlSignals.jump       := decodedControlSignals(5)
+
+  io.branchType := decodedControlSignals(6)
+  io.op1Select  := decodedControlSignals(7)
+  io.op2Select  := decodedControlSignals(8)
+  io.immType    := decodedControlSignals(9)
+  io.ALUop      := decodedControlSignals(10)
+}