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instructions.org
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instructions.org
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--------------------------------------------------------------------------
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4.2. Register-Register Arithmetic Instructions
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--------------------------------------------------------------------------
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* ADD
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- Summary : Addition with 3 GPRs, no overflow exception
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- Assembly : add rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] + R[rs2]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 000 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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* SUB
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- Summary : Subtraction with 3 GPRs, no overflow exception
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- Assembly : sub rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] - R[rs2]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0100000 | rs2 | rs1 | 000 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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* AND
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- Summary : Bitwise logical AND with 3 GPRs
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- Assembly : and rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] & R[rs2]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 111 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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* OR
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- Summary : Bitwise logical OR with 3 GPRs
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- Assembly : or rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] | R[rs2]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 110 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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* XOR
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- Summary : Bitwise logical XOR with 3 GPRs
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- Assembly : xor rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] ^ R[rs2]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 100 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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* SLT
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- Summary : Record result of signed less-than comparison with 2 GPRs
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- Assembly : slt rd, rs1, rs2
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- Semantics : R[rd] = ( R[rs1] <s R[rs2] )
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 010 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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This instruction uses a _signed_ comparison.
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* SLTU
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- Summary : Record result of unsigned less-than comparison with 2 GPRs
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- Assembly : sltu rd, rs1, rs2
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- Semantics : R[rd] = ( R[rs1] <u R[rs2] )
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 011 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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This instruction uses an _unsigned_ comparison.
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* SRA
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- Summary : Shift right arithmetic by register value (sign-extend)
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- Assembly : sra rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] >>> R[rs2][4:0]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0100000 | rs2 | rs1 | 101 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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Note that the hardware should ensure that the sign-bit of R[rs1] is
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extended to the right as it does the right shift. The hardware _must_
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only use the bottom five bits of R[rs2] when performing the shift.
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* SRL
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- Summary : Shift right logical by register value (append zeroes)
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- Assembly : srl rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] >> R[rs2][4:0]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 101 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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Note that the hardware should append zeros to the left as it does the
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right shift. The hardware _must_ only use the bottom five bits of R[rs2]
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when performing the shift.
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* SLL
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- Summary : Shift left logical by register value (append zeroes)
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- Assembly : sll rd, rs1, rs2
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- Semantics : R[rd] = R[rs1] << R[rs2][4:0]
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- Format : R-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | rs2 | rs1 | 001 | rd | 0110011 |
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+------------+---------+---------+------+---------+-------------+
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Note that the hardware should append zeros to the right as it does the
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left shift. The hardware _must_ only use the bottom five bits of R[rs2]
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when performing the shift.
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--------------------------------------------------------------------------
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4.3. Register-Immediate Arithmetic Instructions
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--------------------------------------------------------------------------
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* ADDI
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- Summary : Add constant, no overflow exception
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- Assembly : addi rd, rs1, imm
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- Semantics : R[rd] = R[rs1] + sext(imm)
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 000 | rd | 0010011 |
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+----------------------+---------+------+---------+-------------+
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* ANDI
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- Summary : Bitwise logical AND with constant
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- Assembly : andi rd, rs1, imm
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- Semantics : R[rd] = R[rs1] & sext(imm)
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 111 | rd | 0010011 |
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+----------------------+---------+------+---------+-------------+
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* ORI
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- Summary : Bitwise logical OR with constant
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- Assembly : ori rd, rs1, imm
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- Semantics : R[rd] = R[rs1] | sext(imm)
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 110 | rd | 0010011 |
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+----------------------+---------+------+---------+-------------+
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* XORI
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- Summary : Bitwise logical XOR with constant
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- Assembly : xori rd, rs1, imm
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- Semantics : R[rd] = R[rs1] ^ sext(imm)
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 100 | rd | 0010011 |
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+----------------------+---------+------+---------+-------------+
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* SLTI
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- Summary : Set GPR if source GPR < constant, signed comparison
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- Assembly : slti rd, rs1, imm
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- Semantics : R[rd] = ( R[rs1] <s sext(imm) )
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 010 | rd | 0010011 |
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+----------------------+---------+------+---------+-------------+
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* SLTIU
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- Summary : Set GPR if source GPR is < constant, unsigned comparison
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- Assembly : sltiu rd, rs1, imm
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- Semantics : R[rd] = ( R[rs1] <u sext(imm) )
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 011 | rd | 0010011 |
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+----------------------+---------+------+---------+-------------+
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* SRAI
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- Summary : Shift right arithmetic by constant (sign-extend)
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- Assembly : srai rd, rs1, imm
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- Semantics : R[rd] = R[rs1] >>> imm
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- Format : I-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0100000 | imm | rs1 | 101 | rd | 0010011 |
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+------------+---------+---------+------+---------+-------------+
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Note that the hardware should ensure that the sign-bit of R[rs1] is
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extended to the right as it does the right shift.
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* SRLI
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- Summary : Shift right logical by constant (append zeroes)
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- Assembly : srli rd, rs1, imm
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- Semantics : R[rd] = R[rs1] >> imm
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- Format : I-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | imm | rs1 | 101 | rd | 0010011 |
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+------------+---------+---------+------+---------+-------------+
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Note that the hardware should append zeros to the left as it does the
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right shift.
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* SLLI
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- Summary : Shift left logical constant (append zeroes)
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- Assembly : slli rd, rs1, imm
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- Semantics : R[rd] = R[rs1] << imm
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- Format : I-type
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| 0000000 | imm | rs1 | 001 | rd | 0010011 |
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+------------+---------+---------+------+---------+-------------+
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Note that the hardware should append zeros to the right as it does the
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left shift.
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* LUI
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- Summary : Load constant into upper bits of word
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- Assembly : lui rd, imm
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- Semantics : R[rd] = imm << 12
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- Format : U-type, U-immediate
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31 11 7 6 0
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+---------------------------------------+---------+-------------+
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| imm | rd | 0110111 |
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+---------------------------------------+---------+-------------+
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* AUIPC
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- Summary : Load PC + constant into upper bits of word
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- Assembly : auipc rd, imm
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- Semantics : R[rd] = PC + ( imm << 12 )
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- Format : U-type, U-immediate
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31 11 7 6 0
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+---------------------------------------+---------+-------------+
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| imm | rd | 0010111 |
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+---------------------------------------+---------+-------------+
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--------------------------------------------------------------------------
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4.4. Memory Instructions
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--------------------------------------------------------------------------
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* LW
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- Summary : Load word from memory
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- Assembly : lw rd, imm(rs1)
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- Semantics : R[rd] = M_4B[ R[rs1] + sext(imm) ]
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- Format : I-type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 010 | rd | 0000011 |
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+----------------------+---------+------+---------+-------------+
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All addresses used with LW instructions must be four-byte aligned. This
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means the bottom two bits of every effective address (i.e., after the
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base address is added to the offset) will always be zero.
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* SW
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- Summary : Store word into memory
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- Assembly : sw rs2, imm(rs1)
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- Semantics : M_4B[ R[rs1] + sext(imm) ] = R[rs2]
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- Format : S-type, S-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 010 | imm | 0100011 |
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+------------+---------+---------+------+---------+-------------+
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All addresses used with SW instructions must be four-byte aligned. This
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means the bottom two bits of every effective address (i.e., after the
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base address is added to the offset) will always be zero.
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--------------------------------------------------------------------------
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4.5. Unconditional Jump Instructions
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--------------------------------------------------------------------------
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* JAL
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- Summary : Jump to address and place return address in GPR
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- Assembly : jal rd, imm
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- Semantics : R[rd] = PC + 4; PC = PC + sext(imm)
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- Format : U-type, J-immediate
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31 11 7 6 0
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+---------------------------------------+---------+-------------+
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| imm | rd | 1101111 |
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+---------------------------------------+---------+-------------+
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* JALR
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- Summary : Jump to address and place return address in GPR
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- Assembly : jalr rd, rs1, imm
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- Semantics : R[rd] = PC + 4; PC = ( R[rs1] + sext(imm) ) & 0xfffffffe
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- Format : I-Type, I-immediate
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31 20 19 15 14 12 11 7 6 0
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+----------------------+---------+------+---------+-------------+
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| imm | rs1 | 000 | rd | 1100111 |
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+----------------------+---------+------+---------+-------------+
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Note that the target address is obtained by adding the 12-bit signed
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I-immediate to the value in register rs1, then setting the
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least-significant bit of the result to zero. In other words, the JALR
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instruction ignores the lowest bit of the calculated target address.
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JALR is used when we want to call different subroutines.
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Consider this jump table:
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mul:
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j mulInt
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j mulFloat
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j mulDouble
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depending on the value in rs1 we can select which subroutine to call
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--------------------------------------------------------------------------
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4.6. Conditional Branch Instructions
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--------------------------------------------------------------------------
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* BEQ
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- Summary : Branch if 2 GPRs are equal
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- Assembly : beq rs1, rs2, imm
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- Semantics : PC = ( R[rs1] == R[rs2] ) ? PC + sext(imm) : PC + 4
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- Format : S-type, B-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 000 | imm | 1100011 |
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+------------+---------+---------+------+---------+-------------+
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* BNE
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- Summary : Branch if 2 GPRs are not equal
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- Assembly : bne rs1, rs2, imm
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- Semantics : PC = ( R[rs1] != R[rs2] ) ? PC + sext(imm) : PC + 4
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- Format : S-type, B-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 001 | imm | 1100011 |
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+------------+---------+---------+------+---------+-------------+
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* BLT
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- Summary : Branch based on signed comparison of two GPRs
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- Assembly : blt rs1, rs2, imm
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- Semantics : PC = ( R[rs1] <s R[rs2] ) ? PC + sext(imm) : PC + 4
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- Format : S-type, B-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 100 | imm | 1100011 |
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+------------+---------+---------+------+---------+-------------+
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This instruction uses a _signed_ comparison.
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* BGE
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- Summary : Branch based on signed comparison of two GPRs
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- Assembly : bge rs1, rs2, imm
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- Semantics : PC = ( R[rs1] >=s R[rs2] ) ? PC + sext(imm) : PC + 4
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- Format : S-type, B-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 101 | imm | 1100011 |
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+------------+---------+---------+------+---------+-------------+
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This instruction uses a _signed_ comparison.
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* BLTU
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- Summary : Branch based on unsigned comparison of two GPRs
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- Assembly : bltu rs1, rs2, imm
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- Semantics : PC = ( R[rs1] <u R[rs2] ) ? PC + sext(imm) : PC + 4
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- Format : S-type, B-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 110 | imm | 1100011 |
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+------------+---------+---------+------+---------+-------------+
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This instruction uses an _unsigned_ comparison.
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* BGEU
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- Summary : Branch based on unsigned comparison of two GPRs
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- Assembly : bgeu rs1, rs2, imm
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- Semantics : PC = ( R[rs1] >=u R[rs2] ) ? PC + sext(imm) : PC + 4
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- Format : S-type, B-immediate
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31 25 24 20 19 15 14 12 11 7 6 0
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+------------+---------+---------+------+---------+-------------+
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| imm | rs2 | rs1 | 111 | imm | 1100011 |
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+------------+---------+---------+------+---------+-------------+
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This instruction uses an _unsigned_ comparison.
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