kaholaz/TDT4255
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This commit is contained in:
Sebastian Bugge 2024-10-04 02:16:17 +02:00
parent 934593fb6f
commit 92d0dfd9eb
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
9 changed files with 102 additions and 32 deletions
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12
src/main/scala/IDBarrier.scala
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@ -10,10 +10,14 @@ class IDBarrier extends MultiIOModule {
val op1out = Output(SInt(32.W))
val op2in = Input(SInt(32.W))
val op2out = Output(SInt(32.W))
val r1ValueIn = Input(UInt(32.W))
val r1ValueOut = Output(UInt(32.W))
val r2ValueIn = Input(UInt(32.W))
val r2ValueOut = Output(UInt(32.W))
val ALUopIn = Input(UInt(4.W))
val ALUopOut = Output(UInt(4.W))
val branchTypeIn = Input(UInt(3.W))
val branchTypeOut = Output(UInt(3.W))
val writeAddrIn = Input(UInt(5.W))
val writeAddrOut = Output(UInt(5.W))
val writeEnableIn = Input(Bool())
@ -32,6 +36,10 @@ class IDBarrier extends MultiIOModule {
op2 := io.op2in
io.op2out := op2
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := io.r1ValueIn
io.r1ValueOut := r1Value
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := io.r2ValueIn
io.r2ValueOut := r2Value
@ -40,6 +48,10 @@ class IDBarrier extends MultiIOModule {
ALUop := io.ALUopIn
io.ALUopOut := ALUop
val branchType = RegInit(UInt(5.W), 0.U)
branchType := io.branchTypeIn
io.branchTypeOut := branchType
val writeAddr = RegInit(UInt(5.W), 0.U)
writeAddr := io.writeAddrIn
io.writeAddrOut := writeAddr