kaholaz/TDT4255
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This commit is contained in:
Sebastian Bugge 2024-10-04 02:16:17 +02:00
parent 934593fb6f
commit 92d0dfd9eb
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
9 changed files with 102 additions and 32 deletions
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4
src/main/scala/ID.scala
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@ -22,6 +22,7 @@ class InstructionDecode extends MultiIOModule {
val pc = Input(UInt(32.W))
val op1 = Output(SInt(32.W))
val op2 = Output(SInt(32.W))
val r1Value = Output(UInt(32.W))
val r2Value = Output(UInt(32.W))
val ALUOp = Output(UInt(4.W))
val writeAddrIn = Input(UInt(5.W))
@ -31,6 +32,7 @@ class InstructionDecode extends MultiIOModule {
val writeData = Input(UInt(32.W))
val memWrite = Output(Bool())
val memRead = Output(Bool())
val branchType = Output(UInt(3.W))
}
)
@ -68,9 +70,11 @@ class InstructionDecode extends MultiIOModule {
Op2Select.rs2 -> registers.io.readData2.asSInt(),
)
io.op2 := MuxLookup(decoder.op2Select, 0.S(32.W), select2Map)
io.r1Value := registers.io.readData1
io.r2Value := registers.io.readData2
io.ALUOp := decoder.ALUop
io.branchType := decoder.branchType
io.writeAddrOut := decoder.instruction.registerRd
io.writeEnableOut := decoder.controlSignals.regWrite
io.memRead := decoder.controlSignals.memRead