Add more theory

theory2.org

@@ -1,4 +1,36 @@
-* Question 1 - Benchmarking
+* Question 1 - Hazards
+  For the following program describe each hazard with type (data or control), line number and a
+  small (max one sentence) description
+
+** program 1
+  #+begin_src asm
+    addi t0,   zero,  10
+    addi t1,   zero,  20
+    sub  t1,   t1,    t0
+    beq  t1,   zero, .L2
+    jr   ra
+  #+end_src
+
+** program 2
+  #+begin_src asm
+    addi t0,   zero,  10
+    lw   t0,   10(t0)
+    beq  t0,   zero,  .L3
+    jr   ra
+  #+end_src
+
+** program 3
+  #+begin_src asm
+  lw   t0,   0(t0)
+  lw   t1,   4(t0)
+  sw   t0,   8(t1)
+  lw   t1,   12(t0)
+  beq  t0,   t1,  .L3
+  jr   ra
+  #+end_src
+
+* Question 2 - ???
+* Question 3 - Benchmarking
   In order to gauge the performance increase from adding branch predictors it is necessary to do some testing.
   Rather than writing a test from scratch it is better to use the tester already in use in the test harness.
   When running a program the VM outputs a log of all events, including which branches have been taken and which
@@ -60,6 +92,7 @@
   }
   #+END_SRC
 
+** TODO Branch predictor is underspecified, needs to be cleaned up
 ** Your task
    Your job is to implement a test that checks how many misses occur for a 2 bit branch predictor with 4 slots.
    For this task it is probably smart to use something else than a ~Map[(Int, Boolean)]~
@@ -70,7 +103,7 @@
    With a 2 bit 4 slot scheme, how many misses will you incur?
    Answer with a number.
 
-* Question 2 - Cache profiling
+* Question 4 - Cache profiling
   Unlike our design which has a very limited memory pool, real designs have access to vast amounts of memory, offset
   by a steep cost in access latency.
   To amend this a modern processor features several caches where even the smallest fastest cache has more memory than