Add special handlers for shift instructions.
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peteraa
parent
9358c3a6be
commit
8e2d686b5c
8 changed files with 84 additions and 62 deletions
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@ -93,14 +93,17 @@ object Ops {
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def or( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), OR)
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def xor( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), XOR)
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def and( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), AND)
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def sll( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), SLL)
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def srl( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), SRL)
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def sra( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), SRA)
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def slt( rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), SLT)
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def sltu(rd: Int, rs1: Int, imm: Int) = ArithImm(Reg(rd), Reg(rs1), Imm(imm), SLTU)
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def nop = add(0, 0, 0)
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}
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case class ArithImmShift(imm11: Imm, rd: Reg, rs1: Reg, shamt: Imm, op: ArithOp) extends Op with IType
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object ArithImmShift {
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def sll( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Imm(0), Reg(rd), Reg(rs1), Imm(imm), SLL)
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def srl( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Imm(0), Reg(rd), Reg(rs1), Imm(imm), SRL)
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def sra( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Imm(32), Reg(rd), Reg(rs1), Imm(imm), SRA)
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}
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case class LUI(rd: Reg, imm: Imm) extends Op with UType
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case class AUIPC(rd: Reg, imm: Imm) extends Op with UType
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@ -84,9 +84,9 @@ object Parser {
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stringWs("xori") ~> arithImm.mapN{ArithImm.xor},
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stringWs("andi") ~> arithImm.mapN{ArithImm.and},
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stringWs("slli") ~> arithImm.mapN{ArithImm.sll},
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stringWs("srli") ~> arithImm.mapN{ArithImm.srl},
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stringWs("srai") ~> arithImm.mapN{ArithImm.sra},
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stringWs("slli") ~> arithImm.mapN{ArithImmShift.sll},
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stringWs("srli") ~> arithImm.mapN{ArithImmShift.srl},
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stringWs("srai") ~> arithImm.mapN{ArithImmShift.sra},
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stringWs("slti") ~> arithImm.mapN{ArithImm.slt},
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stringWs("sltiu") ~> arithImm.mapN{ArithImm.sltu},
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@ -160,16 +160,16 @@ object Parser {
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SW(placeHolder, 0, 2048),
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LW(placeHolder, rs1.value, (offset & 0xFFFFFF1C)),
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LW(rd.value, rs1.value, (offset & 0xFFFFFF1C) + 4),
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ArithImm.sra(placeHolder, placeHolder, 24),
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ArithImm.sll(rd.value, rd.value, 24),
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ArithImm.sra(rd.value, rd.value, 16),
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ArithImmShift.sra(placeHolder, placeHolder, 24),
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ArithImmShift.sll(rd.value, rd.value, 24),
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ArithImmShift.sra(rd.value, rd.value, 16),
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Arith.add(rd, rd, placeHolder),
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LW(placeHolder, 0, 2048)).reverse
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}
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case (rd, offset, rs1) if (offset % 4 == 2) => {
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List(
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LW(rd, rs1, (offset & 0xFFFFFF1C)),
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ArithImm.sra(rd, rd, 16)
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ArithImmShift.sra(rd, rd, 16)
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).reverse
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}
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@ -177,8 +177,8 @@ object Parser {
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val leftShift = if((offset % 4) == 0) 16 else 8
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List(
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LW(rd, rs1, (offset & 0xFFFFFF1C)),
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ArithImm.sll(rd, rd, leftShift),
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ArithImm.sra(rd, rd, 16),
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ArithImmShift.sll(rd, rd, leftShift),
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ArithImmShift.sra(rd, rd, 16),
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).reverse
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}
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}.map(_.widen[Op]),
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@ -23,16 +23,17 @@ case class VM(
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def stepInstruction: Either[Finished, ExecutionTrace[VM]] = {
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if (pc.value == 0xEB1CEB1C) Left(Success)
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else getOp flatMap {
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case op: Branch => executeBranch(op)
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case op: Arith => executeArith(op)
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case op: ArithImm => executeArithImm(op)
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case op: AUIPC => executeAUIPC(op)
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case op: LUI => executeLUI(op)
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case op: JALR => executeJALR(op)
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case op: JAL => executeJAL(op)
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case op: LW => executeLW(op)
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case op: SW => executeSW(op)
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case DONE => Left(Success)
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case op: Branch => executeBranch(op)
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case op: Arith => executeArith(op)
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case op: ArithImm => executeArithImm(op)
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case op: ArithImmShift => executeArithImmShift(op)
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case op: AUIPC => executeAUIPC(op)
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case op: LUI => executeLUI(op)
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case op: JALR => executeJALR(op)
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case op: JAL => executeJAL(op)
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case op: LW => executeLW(op)
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case op: SW => executeSW(op)
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case DONE => Left(Success)
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}
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}
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@ -75,6 +76,13 @@ case class VM(
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}
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private def executeArithImmShift(op: ArithImmShift) = {
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val (regUpdate, nextRegs) = regs.arithImm(op.rd, op.rs1, op.shamt, op.op.run)
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val nextVM = this.copy(regs = nextRegs)
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Right(step(nextVM, regUpdate.toList:_*))
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}
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private def executeLUI(op: LUI) = {
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val (regUpdate, nextRegs) = regs + (op.rd -> (op.imm.value << 12))
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val nextVM = this.copy(regs = nextRegs)
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@ -125,12 +125,17 @@ object assembler {
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}
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/**
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* Currently not used, thus we allow too larg shifts.
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* Used by SRI, SRAI, SLLI
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*/
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def setShiftTypeImmediate(instruction: Int, immediate: Int): Int = {
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val points = List((24, 5))
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val withField = applyImmediate(5, immediate, points)(instruction)
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withField
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def setShiftTypeImmediate(funct7: Int, shamt: Int, addr: Addr): Int => InstructionFragment = {
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val shamtPoints = List((24, 5))
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val funct7Points = List((31, 6))
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base => {
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val withF7 = applyImmediateU(funct7, funct7Points, addr)(base)
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val withShamt = withF7.flatMap(base2 => applyImmediateU(shamt, shamtPoints, addr)(base2))
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withShamt
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}
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}
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def setOpCode(opcode: Int): Int => Int = setField(0, 7, opcode)
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@ -142,16 +147,17 @@ object assembler {
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def setOpCode(op: Op): Int => Int = op match {
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case x: Branch => setOpCode("1100011".binary)
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case x: Arith => setOpCode("0110011".binary)
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case x: ArithImm => setOpCode("0010011".binary)
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case x: LW => setOpCode("0000011".binary)
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case x: SW => setOpCode("0100011".binary)
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case x: JALR => setOpCode("1100111".binary)
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case x: JAL => setOpCode("1101111".binary)
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case x: AUIPC => setOpCode("0110111".binary)
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case x: LUI => setOpCode("0010111".binary)
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case DONE => setOpCode("0010011".binary) // done is turned into a NOP in the assembler.
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case x: Branch => setOpCode("1100011".binary)
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case x: Arith => setOpCode("0110011".binary)
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case x: ArithImm => setOpCode("0010011".binary)
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case x: ArithImmShift => setOpCode("0010011".binary)
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case x: LW => setOpCode("0000011".binary)
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case x: SW => setOpCode("0100011".binary)
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case x: JALR => setOpCode("1100111".binary)
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case x: JAL => setOpCode("1101111".binary)
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case x: AUIPC => setOpCode("0110111".binary)
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case x: LUI => setOpCode("0010111".binary)
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case DONE => setOpCode("0010011".binary) // done is turned into a NOP in the assembler.
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}
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def setComparisonFunct(cmp: Comparison): Int => Int = cmp match {
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@ -195,7 +201,6 @@ object assembler {
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setRs1(op.rs1.value)
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def assembleSType(op: SType): Int => Int = {
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// say("stype")
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instruction =>
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(setRs1(op.rs1.value) andThen
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setRs2(op.rs2.value))(instruction)
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@ -214,16 +219,17 @@ object assembler {
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def assembleImmediate(op: Op, addr: Addr, labelMap: Map[Label, Addr]): Int => Either[(String, Addr), Int] = op match {
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case DONE => instruction => Right(instruction)
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case op: Arith => instruction => Right(instruction)
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case op: ArithImm => setItypeImmediate(op.imm.value, addr)
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case op: Branch => setBranchDestination(labelMap, op, addr)
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case op: JALR => instruction => labelMap.lift(op.dst).toRight(s"label ${op.dst} not found", addr).flatMap(addr => setItypeImmediate(addr.value, addr)(instruction))
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case op: AUIPC => setUtypeImmediate(op.imm.value, addr)
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case op: LUI => setUtypeImmediate(op.imm.value, addr)
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case op: LW => setItypeImmediate(op.offset.value, addr)
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case op: SW => setStypeImmediate(op.offset.value, addr)
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case op: JAL => instruction => {
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case DONE => instruction => Right(instruction)
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case op: Arith => instruction => Right(instruction)
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case op: ArithImm => setItypeImmediate(op.imm.value, addr)
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case op: ArithImmShift => setShiftTypeImmediate(op.imm11.value, op.shamt.value, addr)
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case op: Branch => setBranchDestination(labelMap, op, addr)
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case op: JALR => instruction => labelMap.lift(op.dst).toRight(s"label ${op.dst} not found", addr).flatMap(addr => setItypeImmediate(addr.value, addr)(instruction))
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case op: AUIPC => setUtypeImmediate(op.imm.value, addr)
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case op: LUI => setUtypeImmediate(op.imm.value, addr)
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case op: LW => setItypeImmediate(op.offset.value, addr)
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case op: SW => setStypeImmediate(op.offset.value, addr)
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case op: JAL => instruction => {
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val addressDistance = labelMap
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.lift(op.dst).toRight(s"label ${op.dst} not found", addr)
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.map(absoluteAddr => absoluteAddr - addr)
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@ -81,16 +81,17 @@ object PrintUtils {
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val UNKNOWN = "UNKNOWN"
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def printInstruction(op: Ops.Op, labelMap: Map[Label, Addr]): fansi.Str = op match {
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case op: Branch => fansi.Color.Red(s"B${op.comp}\t${op.rs1.show}, ${op.rs2.show}, ${op.dst.show}\t[${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: Arith => s"${op.op}\t${op.rd.show}, ${op.rs1.show}, ${op.rs2.show}"
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case op: ArithImm => s"${op.op}I\t${op.rd.show}, ${op.rs1.show}, ${op.imm.show}"
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case op: JALR => fansi.Color.Green(s"JALR\t${op.rd.show}, ${op.rs1.show}, ${op.dst.show}\t[${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: JAL => fansi.Color.Magenta(s"JAL\t${op.rd.show}, ${op.dst.show} [${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: LW => s"LW\t${op.rd.show}, ${op.offset.show}(${op.rs1.show})"
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case op: SW => s"SW\t${op.rs2.show}, ${op.offset.show}(${op.rs1.show})"
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case op: LUI => s"LUI\t${op.rd.show}, ${op.imm.show}"
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case op: AUIPC => s"AUIPC\t${op.rd.show}, ${op.imm.show}"
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case DONE => s"DONE"
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case op: Branch => fansi.Color.Red(s"B${op.comp}\t${op.rs1.show}, ${op.rs2.show}, ${op.dst.show}\t[${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: Arith => s"${op.op}\t${op.rd.show}, ${op.rs1.show}, ${op.rs2.show}"
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case op: ArithImm => s"${op.op}I\t${op.rd.show}, ${op.rs1.show}, ${op.imm.show}"
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case op: ArithImmShift => s"${op.op}I\t${op.rd.show}, ${op.rs1.show}, ${op.shamt.show}"
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case op: JALR => fansi.Color.Green(s"JALR\t${op.rd.show}, ${op.rs1.show}, ${op.dst.show}\t[${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: JAL => fansi.Color.Magenta(s"JAL\t${op.rd.show}, ${op.dst.show} [${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: LW => s"LW\t${op.rd.show}, ${op.offset.show}(${op.rs1.show})"
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case op: SW => s"SW\t${op.rs2.show}, ${op.offset.show}(${op.rs1.show})"
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case op: LUI => s"LUI\t${op.rd.show}, ${op.imm.show}"
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case op: AUIPC => s"AUIPC\t${op.rd.show}, ${op.imm.show}"
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case DONE => s"DONE"
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}
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