Remove MemToReg.
Pretty sure MemToReg is a MIPS relic, it is redundant so long as all memory reads are put into registers.
This commit is contained in:
peteraaser
parent
743734c346
commit
8dc92fb8e1
5 changed files with 100 additions and 35 deletions
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@ -46,13 +46,13 @@ class Decoder() extends Module {
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*/
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val opcodeMap: Array[(BitPat, List[UInt])] = Array(
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// signal memToReg, regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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LW -> List(Y, Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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LW -> List(Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
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SW -> List(N, N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
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SW -> List(N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
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ADD -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
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SUB -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
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ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
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SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
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/**
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TODO: Fill in the blanks
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@ -60,23 +60,22 @@ class Decoder() extends Module {
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)
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val NOP = List(N, N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
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val NOP = List(N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
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val decodedControlSignals = ListLookup(
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io.instruction.asUInt(),
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NOP,
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opcodeMap)
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io.controlSignals.memToReg := decodedControlSignals(0)
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io.controlSignals.regWrite := decodedControlSignals(1)
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io.controlSignals.memRead := decodedControlSignals(2)
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io.controlSignals.memWrite := decodedControlSignals(3)
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io.controlSignals.branch := decodedControlSignals(4)
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io.controlSignals.jump := decodedControlSignals(5)
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io.controlSignals.regWrite := decodedControlSignals(0)
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io.controlSignals.memRead := decodedControlSignals(1)
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io.controlSignals.memWrite := decodedControlSignals(2)
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io.controlSignals.branch := decodedControlSignals(3)
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io.controlSignals.jump := decodedControlSignals(4)
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io.branchType := decodedControlSignals(6)
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io.op1Select := decodedControlSignals(7)
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io.op2Select := decodedControlSignals(8)
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io.immType := decodedControlSignals(9)
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io.ALUop := decodedControlSignals(10)
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io.branchType := decodedControlSignals(5)
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io.op1Select := decodedControlSignals(6)
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io.op2Select := decodedControlSignals(7)
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io.immType := decodedControlSignals(8)
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io.ALUop := decodedControlSignals(9)
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}
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@ -39,7 +39,6 @@ object Instruction {
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class ControlSignals extends Bundle(){
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val memToReg = Bool()
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val regWrite = Bool()
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val memRead = Bool()
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val memWrite = Bool()
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@ -51,7 +50,6 @@ class ControlSignals extends Bundle(){
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object ControlSignals {
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def nop: ControlSignals = {
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val b = Wire(new ControlSignals)
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b.memToReg := false.B
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b.regWrite := false.B
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b.memRead := false.B
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b.memWrite := false.B
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@ -23,6 +23,7 @@ case class TestOptions(
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printVMtrace : Boolean,
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printVMfinal : Boolean,
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printMergedTrace : Boolean,
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printBinary : Boolean,
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nopPadded : Boolean,
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breakPoints : List[Int], // Not implemented
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testName : String,
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@ -35,7 +36,8 @@ case class TestResult(
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program : String,
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vmTrace : String,
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vmFinal : String,
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sideBySide : String
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sideBySide : String,
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binary : String
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)
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object TestRunner {
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@ -59,6 +61,7 @@ object TestRunner {
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val vmTraceString = printVMtrace(trace, program)
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val vmFinalState = finalVM.regs.show
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val traceString = printLogSideBySide(trace, chiselTrace, program)
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val binaryString = printBinary(binary)
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val regError = compareRegs(trace, chiselTrace)
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val memError = compareMem(trace, chiselTrace)
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@ -69,7 +72,8 @@ object TestRunner {
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programString,
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vmTraceString,
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vmFinalState.toString,
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traceString)
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traceString,
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binaryString)
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}
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testResults.left.foreach{ error =>
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@ -79,15 +83,16 @@ object TestRunner {
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testResults.map{ testResults =>
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val successful = List(testResults.regError, testResults.memError).flatten.headOption.map(_ => false).getOrElse(true)
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if(successful)
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say(s"${testOptions.testName} succesful")
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sayGreen(s"${testOptions.testName} succesful")
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else
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say(s"${testOptions.testName} failed")
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sayRed(s"${testOptions.testName} failed")
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if(testOptions.printIfSuccessful && successful){
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if(testOptions.printParsedProgram) say(testResults.program)
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if(testOptions.printVMtrace) say(testResults.vmTrace)
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if(testOptions.printVMfinal) say(testResults.vmFinal)
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if(testOptions.printMergedTrace) say(testResults.sideBySide)
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if(testOptions.printBinary) say(testResults.binary)
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}
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else{
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if(testOptions.printErrors){
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@ -98,6 +103,7 @@ object TestRunner {
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if(testOptions.printVMtrace) say(testResults.vmTrace)
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if(testOptions.printVMfinal) say(testResults.vmFinal)
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if(testOptions.printMergedTrace) say(testResults.sideBySide)
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if(testOptions.printBinary) say(testResults.binary)
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}
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successful
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}.toOption.getOrElse(false)
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85
theory1.org
85
theory1.org
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@ -6,12 +6,15 @@
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when grading these questions, thus even with no implementation at all you
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should still be able to score 100% on the theory questions.
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All questions can be answered in a few sentences. Remember that brevity is the
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soul of wit, and also the key to getting a good score.
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All questions can be answered in a few sentences. Remember that brevity is wit,
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and also the key to getting a good score.
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You should easily be able to fit your entire answer on a single screen.
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** Question 1
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2 points.
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*2 points.*
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*** Part 1
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**** Part 1½
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*½ points.*
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When decoding the BNE branch instruction in the above assembly program
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#+begin_src asm
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bne x6, x2, "loop",
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@ -19,7 +22,21 @@
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In your design, what is the value of each of the control signals below?
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+ memToReg
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+ regWrite
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+ memRead
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+ memWrite
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+ branch
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+ jump
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**** Part 1¼
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*½ points.*
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When decoding the LW instruction in the above assembly program
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#+begin_src asm
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jal x1, 0x10(x1)
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#+end_src
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In your design, what is the value of each of the control signals below?
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+ regWrite
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+ memRead
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+ memWrite
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@ -33,7 +50,6 @@
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*** Part 2
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During execution, at some arbitrary cycle the control signals are:
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+ memToReg = 0
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+ regWrite = 1
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+ memRead = 0
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+ memWrite = 0
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@ -48,7 +64,10 @@
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implementation.
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** Question 2
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4 points.
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*4 points.*
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*NO PARTIAL CREDITS*
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Since you can test your solution with the testing framework I will not offer any
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points for a near correct solution to this problem.
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Reading the binary of a RISC-V program you get the following:
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@ -77,11 +96,23 @@
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#+end_src
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*Your answer should be in the form of a simple asm program.*
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(hint 1: the original asm program had a label, you need to infer where that label was)
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(hint 2: verify your conclusion by assembling your answer)
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+ hint 1:
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the original asm program had a label, you need to infer where that label was
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+ hint 2:
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Verify your conclusion by assembling your answer.
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To do this, make an asm program, place it with the rest of the tests and set
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~printBinary~ to ~true~ in ~singleTestOptions~ in ~Manifest.scala~ which will
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print the full binary of your program.
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As long as your program generates the same binary as the supplied your program
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is correct.
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** Question 3
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4 points.
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*4 points.*
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*NO PARTIAL CREDITS*
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Since you can test your solution with the testing framework I will not offer any
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points for a near correct solution to this problem.
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In order to load a large number LUI and ADDI are used.
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consider the following program
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@ -94,5 +125,37 @@
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#+end_src
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a) Which of these instructions will be split into ADDI LUI pairs?
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b) Why do the two last instructions need to be handled differently from each other?
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(hint: The parser and assembler in the test suite can help you answer this question)
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b) Explain in 3 sentences or less *how* the two last ops are handled differently and *why*.
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+ hint 1:
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The parser and assembler in the test suite can help you answer the first part of
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this question (a).
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Create an asm file, put it with the rest of the tests and run it, setting the correct
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test options in ~singleTestOptions~ defined in ~Manifest.scala~ and observe the output.
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+ hint 2:
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While it's probably easier to solve this problem using the internet, however you
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can also figure out what is happening by browsing the assembler source code which
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will hopefully give you a deeper insight into what is going on here.
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Look at ~Parser.scala~, specifically what happens when an ~li~ instruction is parsed.
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When parsing an instruction the parser first attempts to apply the
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~singleInstruction~ rule, however this only succeeds if the immediate value
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obeys certain restrictions (~nBits <= 12~), if not it fails.
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If the ~singleInstruction~ rule fails the parser then attempts to apply the
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~multipleInstructions~ rule instead which expands operations into a list of real ops.
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When this happens the resulting operations are defined as the following:
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#+begin_src scala
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stringWs("li") ~> (reg <~ sep, (hex | int).map(_.splitHiLo(20))).mapN{ case(rd, (hi, lo)) => {
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List(
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ArithImm.add(rd, rd, lo),
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LUI(rd, if(lo > 0) hi else hi+1),
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)}}.map(_.widen[Op]),
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#+end_src
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This is quite a lot to unpack, but you can focus on the line where the ~LUI~ is constructed.
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~hi~ and ~lo~ are the results of ~splitHiLo~ which splits a 32 bit word into a 12 bit and a
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20 bit.
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Try this for yourself on paper; what happens when ~lo~ ends up being a negative number?
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What is the interplay between incrementing ~hi~ with 1 and adding a ~lo~ that is represented
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as a negative value?
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@ -46,7 +46,6 @@
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rs1: 4 || rs1: 4 || rs1: 1
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rs2: 5 || rs2: 6 || rs2: 2
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rd: 6 || rd: 4 || rd: 5
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memToReg = false || memToReg = false || memToReg = false
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regWrite = true || regWrite = false || regWrite = true
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memWrite = false || memWrite = false || memWrite = false
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branch = false || branch = true || branch = false
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