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Remove MemToReg.

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Pretty sure MemToReg is a MIPS relic, it is redundant so long as
all memory reads are put into registers.
This commit is contained in:
peteraaser 2020-06-02 14:58:06 +02:00
parent 743734c346
commit 8dc92fb8e1
5 changed files with 100 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

33
src/main/scala/Decoder.scala
View file

@ -46,13 +46,13 @@ class Decoder() extends Module {
*/
val opcodeMap: Array[(BitPat, List[UInt])] = Array(
// signal memToReg, regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
LW -> List(Y, Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
LW -> List(Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
SW -> List(N, N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
SW -> List(N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
ADD -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
SUB -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
/**
TODO: Fill in the blanks
@ -60,23 +60,22 @@ class Decoder() extends Module {
)
val NOP = List(N, N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
val NOP = List(N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
val decodedControlSignals = ListLookup(
io.instruction.asUInt(),
NOP,
opcodeMap)
io.controlSignals.memToReg := decodedControlSignals(0)
io.controlSignals.regWrite := decodedControlSignals(1)
io.controlSignals.memRead := decodedControlSignals(2)
io.controlSignals.memWrite := decodedControlSignals(3)
io.controlSignals.branch := decodedControlSignals(4)
io.controlSignals.jump := decodedControlSignals(5)
io.controlSignals.regWrite := decodedControlSignals(0)
io.controlSignals.memRead := decodedControlSignals(1)
io.controlSignals.memWrite := decodedControlSignals(2)
io.controlSignals.branch := decodedControlSignals(3)
io.controlSignals.jump := decodedControlSignals(4)
io.branchType := decodedControlSignals(6)
io.op1Select := decodedControlSignals(7)
io.op2Select := decodedControlSignals(8)
io.immType := decodedControlSignals(9)
io.ALUop := decodedControlSignals(10)
io.branchType := decodedControlSignals(5)
io.op1Select := decodedControlSignals(6)
io.op2Select := decodedControlSignals(7)
io.immType := decodedControlSignals(8)
io.ALUop := decodedControlSignals(9)
}

2
src/main/scala/ToplevelSignals.scala
View file

@ -39,7 +39,6 @@ object Instruction {
class ControlSignals extends Bundle(){
val memToReg = Bool()
val regWrite = Bool()
val memRead = Bool()
val memWrite = Bool()
@ -51,7 +50,6 @@ class ControlSignals extends Bundle(){
object ControlSignals {
def nop: ControlSignals = {
val b = Wire(new ControlSignals)
b.memToReg := false.B
b.regWrite := false.B
b.memRead := false.B
b.memWrite := false.B

14
src/test/scala/RISCV/testRunner.scala
View file

@ -23,6 +23,7 @@ case class TestOptions(
printVMtrace : Boolean,
printVMfinal : Boolean,
printMergedTrace : Boolean,
printBinary : Boolean,
nopPadded : Boolean,
breakPoints : List[Int], // Not implemented
testName : String,
@ -35,7 +36,8 @@ case class TestResult(
program : String,
vmTrace : String,
vmFinal : String,
sideBySide : String
sideBySide : String,
binary : String
)
object TestRunner {
@ -59,6 +61,7 @@ object TestRunner {
val vmTraceString = printVMtrace(trace, program)
val vmFinalState = finalVM.regs.show
val traceString = printLogSideBySide(trace, chiselTrace, program)
val binaryString = printBinary(binary)
val regError = compareRegs(trace, chiselTrace)
val memError = compareMem(trace, chiselTrace)
@ -69,7 +72,8 @@ object TestRunner {
programString,
vmTraceString,
vmFinalState.toString,
traceString)
traceString,
binaryString)
}
testResults.left.foreach{ error =>
@ -79,15 +83,16 @@ object TestRunner {
testResults.map{ testResults =>
val successful = List(testResults.regError, testResults.memError).flatten.headOption.map(_ => false).getOrElse(true)
if(successful)
say(s"${testOptions.testName} succesful")
sayGreen(s"${testOptions.testName} succesful")
else
say(s"${testOptions.testName} failed")
sayRed(s"${testOptions.testName} failed")
if(testOptions.printIfSuccessful && successful){
if(testOptions.printParsedProgram) say(testResults.program)
if(testOptions.printVMtrace) say(testResults.vmTrace)
if(testOptions.printVMfinal) say(testResults.vmFinal)
if(testOptions.printMergedTrace) say(testResults.sideBySide)
if(testOptions.printBinary) say(testResults.binary)
}
else{
if(testOptions.printErrors){
@ -98,6 +103,7 @@ object TestRunner {
if(testOptions.printVMtrace) say(testResults.vmTrace)
if(testOptions.printVMfinal) say(testResults.vmFinal)
if(testOptions.printMergedTrace) say(testResults.sideBySide)
if(testOptions.printBinary) say(testResults.binary)
}
successful
}.toOption.getOrElse(false)