kaholaz/TDT4255
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Sebastian Bugge 2024-11-01 03:32:59 +01:00
parent 800e7b6eb0
commit 804e1ed2e6
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
4 changed files with 10 additions and 5 deletions
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8
src/main/scala/ID.scala
View file

@ -86,7 +86,6 @@ class InstructionDecode extends MultiIOModule {
io.r2Address := registers.io.readAddress2 io.r2Address := registers.io.readAddress2
io.ALUOp := decoder.ALUop io.ALUOp := decoder.ALUop
io.branchType := decoder.branchType
io.writeAddrOut := decoder.instruction.registerRd io.writeAddrOut := decoder.instruction.registerRd
val stallsRemaining = RegInit(UInt(4.W), 0.U) val stallsRemaining = RegInit(UInt(4.W), 0.U)
@ -97,13 +96,18 @@ class InstructionDecode extends MultiIOModule {
Mux( Mux(
decoder.controlSignals.memRead, decoder.controlSignals.memRead,
1.U, 1.U,
Mux(
decoder.controlSignals.branch,
3.U,
0.U 0.U
)
)) ))
val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay || decoder.controlSignals.branch && !stallDelay
io.stall := stall io.stall := stall
io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump) io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
io.branchType := Mux(stallDelay, branchType.DC, decoder.branchType)
io.returnAddr := io.pc + 4.U io.returnAddr := io.pc + 4.U
io.writeEnableOut := Mux(stallDelay, false.B, decoder.controlSignals.regWrite) io.writeEnableOut := Mux(stallDelay, false.B, decoder.controlSignals.regWrite)

2
src/main/scala/IF.scala
View file

@ -48,7 +48,7 @@ class InstructionFetch extends MultiIOModule {
*/ */
io.PC := PC io.PC := PC
IMEM.io.instructionAddress := PC IMEM.io.instructionAddress := PC
PC := Mux(io.stall, PC, Mux(io.branch, io.branchAddress, PC + 4.U)) PC := Mux(io.branch, io.branchAddress, Mux(io.stall, PC, PC + 4.U))
val instruction = Wire(new Instruction) val instruction = Wire(new Instruction)
instruction := IMEM.io.instruction.asTypeOf(new Instruction) instruction := IMEM.io.instruction.asTypeOf(new Instruction)

1
src/test/resources/tests/branch.s
View file

@ -4,4 +4,5 @@ main:
loop: loop:
addi x2, x2, 1 addi x2, x2, 1
blt x2, x1, loop blt x2, x1, loop
nop
done done

2
src/test/scala/Manifest.scala
View file

@ -19,7 +19,7 @@ import LogParser._
object Manifest { object Manifest {
val singleTest = "forward1.s" val singleTest = "branch.s"
val nopPadded = false val nopPadded = false