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This commit is contained in:
Sebastian Bugge 2024-11-01 03:32:59 +01:00
parent 800e7b6eb0
commit 804e1ed2e6
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
4 changed files with 10 additions and 5 deletions
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10
src/main/scala/ID.scala
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@ -86,7 +86,6 @@ class InstructionDecode extends MultiIOModule {
io.r2Address := registers.io.readAddress2
io.ALUOp := decoder.ALUop
io.branchType := decoder.branchType
io.writeAddrOut := decoder.instruction.registerRd
val stallsRemaining = RegInit(UInt(4.W), 0.U)
@ -97,13 +96,18 @@ class InstructionDecode extends MultiIOModule {
Mux(
decoder.controlSignals.memRead,
1.U,
0.U
Mux(
decoder.controlSignals.branch,
3.U,
0.U
)
))
val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay
val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay || decoder.controlSignals.branch && !stallDelay
io.stall := stall
io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
io.branchType := Mux(stallDelay, branchType.DC, decoder.branchType)
io.returnAddr := io.pc + 4.U
io.writeEnableOut := Mux(stallDelay, false.B, decoder.controlSignals.regWrite)