From 70556c496cdd88f0d0ea18613ec2a6bad1d4ea94 Mon Sep 17 00:00:00 2001
From: peteraa <peteraaser@gmail.com>
Date: Wed, 11 Sep 2019 17:19:41 +0200
Subject: [PATCH] Add theory exercises

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+* Theory question EX1
+  
+  Keep in mind that your design and your implementation are separate entities,
+  thus you should answer these questions based on your ideal design, not your
+  finished implementation. Consequently I will not consider your implementation
+  when grading these questions, thus even with no implementation at all you
+  should still be able to score 100% on the theory questions.
+  
+  All questions can be answered in a few sentences. Remember that brevity is the
+  soul of wit, and also the key to getting a good score.
+
+** Question 1
+   2 points.
+*** Part 1
+    When decoding the BNE branch instruction in the above assembly program
+    #+begin_src asm
+    bne x6, x2, "loop",
+    #+end_src
+    
+    In your design, what is the value of each of the control signals below?
+     
+    + memToReg
+    + regWrite
+    + memRead
+    + memWrite
+    + branch
+    + jump
+
+    Keep in mind that your design and your implementation are separate entities, thus
+    you should answer this question based on your ideal design, not your finished 
+    implementation.
+   
+*** Part 2
+   During execution, at some arbitrary cycle the control signals are:
+
+   + memToReg = 0
+   + regWrite = 1
+   + memRead  = 0
+   + memWrite = 0
+   + branch   = 0
+   + jump     = 1
+   
+   In your design, which intruction(s) could be executing?
+   
+
+   Keep in mind that your design and your implementation are separate entities, thus
+   you should answer this question based on your ideal design, not your finished 
+   implementation.
+   
+** Question 2
+   4 points.
+
+   Reading the binary of a RISC-V program you get the following:
+
+   #+begin_src text
+   0x0:  0x00a00293   --   0000 0000 1010 0000 0000 0010 1001 0011
+   0x4:  0x01400313   --   0000 0001 0100 0000 0000 0011 0001 0011
+   0x8:  0xfff30313   --   1111 1111 1111 0011 0000 0011 0001 0011
+   0xc:  0x00628463   --   0000 0000 0110 0010 1000 0100 0110 0011
+   0x10: 0xff9ff06f   --   1111 1111 1001 1111 1111 0000 0110 1111
+   #+end_src
+
+   For each instruction describe the format and name and corresponding RISC-V source
+   To give you an idea on how decoding would work, here is the decoding of 0x40635293:
+
+   #+begin_src text
+   0x40635293   --   0100 0000 0110 0011 0101 0010 1001 0011
+
+   Opcode: 0010011 => Format is IType, thus the funct3 field is used to decode further
+   funct3: 101     => Instruction is of type SRAI, the instruction looks like ~srai rd, rx, imm~
+
+   rs1:    00110   => x6
+   rd:     00101   => x5
+   shamt:  000110  => 6
+   
+   Resulting in ~srai x5, x6, 6~
+   #+end_src
+   
+   *Your answer should be in the form of a simple asm program.*
+   (hint 1: the original asm program had a label, you need to infer where that label was)
+   (hint 2: verify your conclusion by assembling your answer)
+
+** Question 3
+   4 points.
+
+   In order to load a large number LUI and ADDI are used.
+   consider the following program
+   #+begin_src asm
+   li x0, 0xFF
+   li x1, 0x600
+   li x2, 0x8EE
+   li x3, 0xBABEFACE
+   li x4, 0xBABE07CE
+   #+end_src
+   
+   a) Which of these instructions will be split into ADDI LUI pairs?
+   b) Why do the two last instructions need to be handled differently from each other?
+   (hint: The parser and assembler in the test suite can help you answer this question)