From 6fa8d3537a464cfe75c2640ee643fa092f9c1c5c Mon Sep 17 00:00:00 2001
From: peteraa <peteraaser@gmail.com>
Date: Wed, 4 Sep 2019 13:55:05 +0200
Subject: [PATCH] Fix nonexhaustive match causing funct3 to not be applied to
 imm shifts

---
 src/test/scala/RISCV/Ops.scala        |  8 +++----
 src/test/scala/RISCV/assembler.scala  | 34 +++++++++++++--------------
 src/test/scala/RISCV/printUtils.scala |  2 +-
 3 files changed, 21 insertions(+), 23 deletions(-)

diff --git a/src/test/scala/RISCV/Ops.scala b/src/test/scala/RISCV/Ops.scala
index 9158312..f77a351 100644
--- a/src/test/scala/RISCV/Ops.scala
+++ b/src/test/scala/RISCV/Ops.scala
@@ -98,11 +98,11 @@ object Ops {
     def nop = add(0, 0, 0)
   }
 
-  case class ArithImmShift(imm11: Imm, rd: Reg, rs1: Reg, shamt: Imm, op: ArithOp) extends Op with IType
+  case class ArithImmShift(rd: Reg, rs1: Reg, shamt: Imm, op: ArithOp) extends Op with IType
   object ArithImmShift {
-    def sll( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Imm(0), Reg(rd), Reg(rs1), Imm(imm), SLL)
-    def srl( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Imm(0), Reg(rd), Reg(rs1), Imm(imm), SRL)
-    def sra( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Imm(32), Reg(rd), Reg(rs1), Imm(imm), SRA)
+    def sll( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Reg(rd), Reg(rs1), Imm(imm), SLL)
+    def srl( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Reg(rd), Reg(rs1), Imm(imm), SRL)
+    def sra( rd: Int, rs1: Int, imm: Int) = ArithImmShift(Reg(rd), Reg(rs1), Imm(imm), SRA)
   }
 
   case class LUI(rd: Reg, imm: Imm)              extends Op with UType
diff --git a/src/test/scala/RISCV/assembler.scala b/src/test/scala/RISCV/assembler.scala
index 7c4f943..1f7ff49 100644
--- a/src/test/scala/RISCV/assembler.scala
+++ b/src/test/scala/RISCV/assembler.scala
@@ -127,15 +127,9 @@ object assembler {
   /**
     * Used by SRI, SRAI, SLLI
     */
-  def setShiftTypeImmediate(funct7: Int, shamt: Int, addr: Addr): Int => InstructionFragment = {
-    val shamtPoints = List((24, 5))
-    val funct7Points = List((31, 6))
-
-    base => {
-      val withF7 = applyImmediateU(funct7, funct7Points, addr)(base)
-      val withShamt = withF7.flatMap(base2 => applyImmediateU(shamt, shamtPoints, addr)(base2))
-      withShamt
-    }
+  def setShiftTypeImmediate(shamt: Int, addr: Addr): Int => InstructionFragment = {
+    val points = List((24, 5))
+    applyImmediateU(shamt, points, addr)
   }
 
   def setOpCode(opcode: Int): Int => Int = setField(0, 7, opcode)
@@ -222,7 +216,7 @@ object assembler {
     case DONE              => instruction => Right(instruction)
     case op: Arith         => instruction => Right(instruction)
     case op: ArithImm      => setItypeImmediate(op.imm.value, addr)
-    case op: ArithImmShift => setShiftTypeImmediate(op.imm11.value, op.shamt.value, addr)
+    case op: ArithImmShift => setShiftTypeImmediate(op.shamt.value, addr)
     case op: Branch        => setBranchDestination(labelMap, op, addr)
     case op: JALR          => instruction => labelMap.lift(op.dst).toRight(s"label ${op.dst} not found", addr).flatMap(addr => setItypeImmediate(addr.value, addr)(instruction))
     case op: AUIPC         => setUtypeImmediate(op.imm.value, addr)
@@ -252,14 +246,18 @@ object assembler {
     val opcode    = setOpCode(op)
 
     val extras: Int => Int = (instruction: Int) => op match {
-      case op: Branch   => setComparisonFunct(op.comp)(instruction)
-      case op: ArithImm => setArithFunct(op.op)(instruction)
-      case op: Arith    => setArithFunct(op.op)(instruction)
-      case op: JALR     => setFunct3("000".binary)(instruction)
-      case op: LW       => setFunct3("010".binary)(instruction)
-      case op: SW       => setFunct3("010".binary)(instruction)
-      case DONE         => (setFunct3("000".binary) andThen setFunct7("0000000".binary))(instruction)
-      case _            => instruction
+      case op: Branch        => setComparisonFunct(op.comp)(instruction)
+      case op: ArithImm      => setArithFunct(op.op)(instruction)
+      case op: ArithImmShift => setArithFunct(op.op)(instruction)
+      case op: Arith         => setArithFunct(op.op)(instruction)
+      case op: JALR          => setFunct3("000".binary)(instruction)
+      case op: LW            => setFunct3("010".binary)(instruction)
+      case op: SW            => setFunct3("010".binary)(instruction)
+      case DONE              => (setFunct3("000".binary) andThen setFunct7("0000000".binary))(instruction)
+
+      case op: AUIPC         => instruction
+      case op: JAL           => instruction
+      case op: LUI           => instruction
     }
 
     val withOp = opcode(0)
diff --git a/src/test/scala/RISCV/printUtils.scala b/src/test/scala/RISCV/printUtils.scala
index 4c18a8a..f9d37b9 100644
--- a/src/test/scala/RISCV/printUtils.scala
+++ b/src/test/scala/RISCV/printUtils.scala
@@ -119,7 +119,7 @@ object PrintUtils {
 
 
   def printBinary(bin: Map[Addr, Int]): String = {
-    bin.toList.sortBy(_._1.value).map{ case(addr, op) => s"$addr: ${op.hs}" }.mkString("\n","\n","\n")
+    bin.toList.sortBy(_._1.value).map{ case(addr, op) => s"$addr: ${op.hs}\t--\t${op.binary}" }.mkString("\n","\n","\n")
   }