Simplify IDBarrier.
This commit is contained in:
parent
1eefeca2d6
commit
6d6474530c
2 changed files with 38 additions and 58 deletions
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@ -54,6 +54,25 @@ class CPU extends MultiIOModule {
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/**
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/**
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TODO: Your code here
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TODO: Your code here
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*/
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*/
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def forward(data: UInt, addr: UInt, useForward: Bool, mem: Forwarding, wb: Forwarding, id: Forwarding): UInt = {
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Mux(
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!useForward,
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data,
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Mux(
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mem.valid && mem.writeAddr === addr,
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mem.writeData,
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Mux(
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wb.valid && wb.writeAddr === addr,
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wb.writeData,
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Mux(
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id.valid && id.writeAddr === addr,
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id.writeData,
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data,
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)
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)
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)
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)
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}
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IFBarrier.PCin := IF.io.PC
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IFBarrier.PCin := IF.io.PC
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IFBarrier.instructionIn := IF.io.instruction
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IFBarrier.instructionIn := IF.io.instruction
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@ -63,8 +82,8 @@ class CPU extends MultiIOModule {
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IDBarrier.op1in := ID.io.op1
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IDBarrier.op1in := ID.io.op1
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IDBarrier.op2in := ID.io.op2
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IDBarrier.op2in := ID.io.op2
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IDBarrier.isOp1RValue := ID.io.isOp1RValue
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IDBarrier.isOp1RValueIn := ID.io.isOp1RValue
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IDBarrier.isOp2RValue := ID.io.isOp2RValue
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IDBarrier.isOp2RValueIn := ID.io.isOp2RValue
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IDBarrier.r1ValueIn := ID.io.r1Value
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IDBarrier.r1ValueIn := ID.io.r1Value
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IDBarrier.r2ValueIn := ID.io.r2Value
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IDBarrier.r2ValueIn := ID.io.r2Value
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IDBarrier.r1AddressIn := ID.io.r1Address
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IDBarrier.r1AddressIn := ID.io.r1Address
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@ -78,12 +97,12 @@ class CPU extends MultiIOModule {
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IDBarrier.memWriteIn := ID.io.memWrite
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IDBarrier.memWriteIn := ID.io.memWrite
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IDBarrier.memReadIn := ID.io.memRead
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IDBarrier.memReadIn := ID.io.memRead
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EX.io.op1 := IDBarrier.op1out
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EX.io.op1 := forward(IDBarrier.op1out.asUInt(), IDBarrier.r1AddressOut, IDBarrier.isOp1RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.op2 := IDBarrier.op2out
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EX.io.op2 := forward(IDBarrier.op2out.asUInt(), IDBarrier.r2AddressOut, IDBarrier.isOp2RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.ALUOp := IDBarrier.ALUopOut
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EX.io.ALUOp := IDBarrier.ALUopOut
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EX.io.branchType := IDBarrier.branchTypeOut
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EX.io.branchType := IDBarrier.branchTypeOut
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EX.io.rs1ValueIn := IDBarrier.r1ValueOut.asSInt()
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EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.rs2ValueIn := IDBarrier.r2ValueOut.asSInt()
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EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt()
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EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt()
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EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt()
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EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt()
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@ -8,10 +8,12 @@ class IDBarrier extends MultiIOModule {
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new Bundle {
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new Bundle {
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val op1in = Input(SInt(32.W))
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val op1in = Input(SInt(32.W))
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val op1out = Output(SInt(32.W))
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val op1out = Output(SInt(32.W))
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val isOp1RValue = Input(Bool())
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val isOp1RValueIn = Input(Bool())
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val isOp1RValueOut = Output(Bool())
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val op2in = Input(SInt(32.W))
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val op2in = Input(SInt(32.W))
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val op2out = Output(SInt(32.W))
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val op2out = Output(SInt(32.W))
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val isOp2RValue = Input(Bool())
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val isOp2RValueIn = Input(Bool())
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val isOp2RValueOut = Output(Bool())
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val r1ValueIn = Input(UInt(32.W))
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val r1ValueIn = Input(UInt(32.W))
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val r1ValueOut = Output(UInt(32.W))
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val r1ValueOut = Output(UInt(32.W))
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val r1AddressIn = Input(UInt(5.W))
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val r1AddressIn = Input(UInt(5.W))
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@ -36,16 +38,15 @@ class IDBarrier extends MultiIOModule {
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val memReadOut = Output(Bool())
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val memReadOut = Output(Bool())
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val memWriteIn = Input(Bool())
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val memWriteIn = Input(Bool())
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val memWriteOut = Output(Bool())
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val memWriteOut = Output(Bool())
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val forwardMem = Input(new Forwarding)
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val forwardWb = Input(new Forwarding)
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val forwardId = Input(new Forwarding)
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})
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})
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val isOp1RValue = RegInit(Bool(), false.B)
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val isOp1RValue = RegInit(Bool(), false.B)
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isOp1RValue := io.isOp1RValue
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isOp1RValue := io.isOp1RValueIn
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io.isOp1RValueOut := isOp1RValue
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val isOp2RValue = RegInit(Bool(), false.B)
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val isOp2RValue = RegInit(Bool(), false.B)
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isOp2RValue := io.isOp2RValue
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isOp2RValue := io.isOp2RValueIn
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io.isOp2RValueOut := isOp2RValue
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val r2Address = RegInit(UInt(5.W), 0.U)
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val r2Address = RegInit(UInt(5.W), 0.U)
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r2Address := io.r2AddressIn
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r2Address := io.r2AddressIn
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@ -57,59 +58,19 @@ class IDBarrier extends MultiIOModule {
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val op1 = RegInit(SInt(32.W), 0.S)
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val op1 = RegInit(SInt(32.W), 0.S)
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op1 := io.op1in
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op1 := io.op1in
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io.op1out := Mux(
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io.op1out := op1
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isOp1RValue && io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
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io.forwardMem.writeData.asSInt(),
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Mux(
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isOp1RValue && io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
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io.forwardWb.writeData.asSInt(),
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Mux(
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isOp1RValue && io.forwardId.valid && r1Address === io.forwardId.writeAddr,
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io.forwardId.writeData.asSInt(),
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op1.asSInt(),
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)))
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val op2 = RegInit(SInt(32.W), 0.S)
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val op2 = RegInit(SInt(32.W), 0.S)
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op2 := io.op2in
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op2 := io.op2in
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io.op2out := Mux(
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io.op2out := op2
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isOp2RValue && io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
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io.forwardMem.writeData.asSInt(),
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Mux(
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isOp2RValue && io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
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io.forwardWb.writeData.asSInt(),
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Mux(
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isOp2RValue && io.forwardId.valid && r2Address === io.forwardId.writeAddr,
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io.forwardId.writeData.asSInt(),
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op2.asSInt(),
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)))
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val r1Value = RegInit(UInt(32.W), 0.U)
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val r1Value = RegInit(UInt(32.W), 0.U)
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r1Value := io.r1ValueIn
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r1Value := io.r1ValueIn
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io.r1ValueOut := Mux(
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io.r1ValueOut := r1Value
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io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
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io.forwardMem.writeData,
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Mux(
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io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
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io.forwardWb.writeData,
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Mux(
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io.forwardId.valid && r1Address === io.forwardId.writeAddr,
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io.forwardId.writeData,
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r1Value,
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)))
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val r2Value = RegInit(UInt(32.W), 0.U)
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val r2Value = RegInit(UInt(32.W), 0.U)
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r2Value := io.r2ValueIn
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r2Value := io.r2ValueIn
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io.r2ValueOut := Mux(
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io.r2ValueOut := r2Value
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io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
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io.forwardMem.writeData,
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Mux(
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io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
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io.forwardWb.writeData,
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Mux(
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io.forwardId.valid && r2Address === io.forwardId.writeAddr,
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io.forwardId.writeData,
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r2Value,
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)))
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val returnAddr = RegInit(UInt(32.W), 0.U)
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val returnAddr = RegInit(UInt(32.W), 0.U)
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returnAddr := io.returnAddrIn
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returnAddr := io.returnAddrIn
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