kaholaz/TDT4255
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Simplify IDBarrier.

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This commit is contained in:
Sebastian Bugge 2024-11-07 23:51:17 +01:00
parent 1eefeca2d6
commit 6d6474530c
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
2 changed files with 38 additions and 58 deletions
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65
src/main/scala/IDBarrier.scala
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@ -8,10 +8,12 @@ class IDBarrier extends MultiIOModule {
new Bundle {
val op1in = Input(SInt(32.W))
val op1out = Output(SInt(32.W))
val isOp1RValue = Input(Bool())
val isOp1RValueIn = Input(Bool())
val isOp1RValueOut = Output(Bool())
val op2in = Input(SInt(32.W))
val op2out = Output(SInt(32.W))
val isOp2RValue = Input(Bool())
val isOp2RValueIn = Input(Bool())
val isOp2RValueOut = Output(Bool())
val r1ValueIn = Input(UInt(32.W))
val r1ValueOut = Output(UInt(32.W))
val r1AddressIn = Input(UInt(5.W))
@ -36,16 +38,15 @@ class IDBarrier extends MultiIOModule {
val memReadOut = Output(Bool())
val memWriteIn = Input(Bool())
val memWriteOut = Output(Bool())
val forwardMem = Input(new Forwarding)
val forwardWb = Input(new Forwarding)
val forwardId = Input(new Forwarding)
})
val isOp1RValue = RegInit(Bool(), false.B)
isOp1RValue := io.isOp1RValue
isOp1RValue := io.isOp1RValueIn
io.isOp1RValueOut := isOp1RValue
val isOp2RValue = RegInit(Bool(), false.B)
isOp2RValue := io.isOp2RValue
isOp2RValue := io.isOp2RValueIn
io.isOp2RValueOut := isOp2RValue
val r2Address = RegInit(UInt(5.W), 0.U)
r2Address := io.r2AddressIn
@ -57,59 +58,19 @@ class IDBarrier extends MultiIOModule {
val op1 = RegInit(SInt(32.W), 0.S)
op1 := io.op1in
io.op1out := Mux(
isOp1RValue && io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
io.forwardMem.writeData.asSInt(),
Mux(
isOp1RValue && io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
io.forwardWb.writeData.asSInt(),
Mux(
isOp1RValue && io.forwardId.valid && r1Address === io.forwardId.writeAddr,
io.forwardId.writeData.asSInt(),
op1.asSInt(),
)))
io.op1out := op1
val op2 = RegInit(SInt(32.W), 0.S)
op2 := io.op2in
io.op2out := Mux(
isOp2RValue && io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
io.forwardMem.writeData.asSInt(),
Mux(
isOp2RValue && io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
io.forwardWb.writeData.asSInt(),
Mux(
isOp2RValue && io.forwardId.valid && r2Address === io.forwardId.writeAddr,
io.forwardId.writeData.asSInt(),
op2.asSInt(),
)))
io.op2out := op2
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := io.r1ValueIn
io.r1ValueOut := Mux(
io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
io.forwardMem.writeData,
Mux(
io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
io.forwardWb.writeData,
Mux(
io.forwardId.valid && r1Address === io.forwardId.writeAddr,
io.forwardId.writeData,
r1Value,
)))
io.r1ValueOut := r1Value
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := io.r2ValueIn
io.r2ValueOut := Mux(
io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
io.forwardMem.writeData,
Mux(
io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
io.forwardWb.writeData,
Mux(
io.forwardId.valid && r2Address === io.forwardId.writeAddr,
io.forwardId.writeData,
r2Value,
)))
io.r2ValueOut := r2Value
val returnAddr = RegInit(UInt(32.W), 0.U)
returnAddr := io.returnAddrIn