kaholaz/TDT4255
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Simplify IDBarrier.

Browse source
This commit is contained in:
Sebastian Bugge 2024-11-07 23:51:17 +01:00
parent 1eefeca2d6
commit 6d6474530c
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
2 changed files with 38 additions and 58 deletions
Download patch file Download diff file Expand all files Collapse all files

31
src/main/scala/CPU.scala
View file

@ -54,6 +54,25 @@ class CPU extends MultiIOModule {
/**
TODO: Your code here
*/
def forward(data: UInt, addr: UInt, useForward: Bool, mem: Forwarding, wb: Forwarding, id: Forwarding): UInt = {
Mux(
!useForward,
data,
Mux(
mem.valid && mem.writeAddr === addr,
mem.writeData,
Mux(
wb.valid && wb.writeAddr === addr,
wb.writeData,
Mux(
id.valid && id.writeAddr === addr,
id.writeData,
data,
)
)
)
)
}
IFBarrier.PCin := IF.io.PC
IFBarrier.instructionIn := IF.io.instruction
@ -63,8 +82,8 @@ class CPU extends MultiIOModule {
IDBarrier.op1in := ID.io.op1
IDBarrier.op2in := ID.io.op2
IDBarrier.isOp1RValue := ID.io.isOp1RValue
IDBarrier.isOp2RValue := ID.io.isOp2RValue
IDBarrier.isOp1RValueIn := ID.io.isOp1RValue
IDBarrier.isOp2RValueIn := ID.io.isOp2RValue
IDBarrier.r1ValueIn := ID.io.r1Value
IDBarrier.r2ValueIn := ID.io.r2Value
IDBarrier.r1AddressIn := ID.io.r1Address
@ -78,12 +97,12 @@ class CPU extends MultiIOModule {
IDBarrier.memWriteIn := ID.io.memWrite
IDBarrier.memReadIn := ID.io.memRead
EX.io.op1 := IDBarrier.op1out
EX.io.op2 := IDBarrier.op2out
EX.io.op1 := forward(IDBarrier.op1out.asUInt(), IDBarrier.r1AddressOut, IDBarrier.isOp1RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EX.io.op2 := forward(IDBarrier.op2out.asUInt(), IDBarrier.r2AddressOut, IDBarrier.isOp2RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EX.io.ALUOp := IDBarrier.ALUopOut
EX.io.branchType := IDBarrier.branchTypeOut
EX.io.rs1ValueIn := IDBarrier.r1ValueOut.asSInt()
EX.io.rs2ValueIn := IDBarrier.r2ValueOut.asSInt()
EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt()
EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt()