From 6223a71046a8ac6651c642ef0c92d378564c1d11 Mon Sep 17 00:00:00 2001 From: peteraa Date: Mon, 4 Nov 2019 16:19:47 +0100 Subject: [PATCH] aaaa --- theory2.org | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/theory2.org b/theory2.org index e534f30..78b3ec9 100644 --- a/theory2.org +++ b/theory2.org @@ -247,8 +247,8 @@ ** Your task Your job is to implement a model that tests how many delay cycles will occur for a cache which: + Follows a 2-way associative scheme - + Block size is 4 words (128 bits) - + Is write-through write no-allocate + + Block size is 4 words (128 bits) (total cache size: a whopping 256 bits) + + Is write-through write no-allocate (this means that you can ignore stores, only loads will affect the cache) + Eviction policy is LRU (least recently used) Your answer should be the number of cache miss latency cycles when using this cache.