Working adder.

src/main/scala/IFBarrier.scala

@@ -0,0 +1,20 @@
+package FiveStage
+
+import chisel3._
+import chisel3.experimental.MultiIOModule
+
+class IFBarrier extends MultiIOModule {
+  val io = IO(
+    new Bundle {
+      val PCin = Input(UInt(32.W))
+      val PCout = Output(UInt(32.W))
+      val instructionIn = Input(new Instruction)
+      val instructionOut = Output(new Instruction)
+    })
+
+  val PC = RegInit(UInt(32.W), 0.U)
+  PC := io.PCin
+  io.PCout := PC
+
+  io.instructionOut := io.instructionIn
+}