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Working adder.

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This commit is contained in:
Sebastian Bugge 2024-09-27 04:22:10 +02:00
parent 88cab777f9
commit 44ccf12cad
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
9 changed files with 214 additions and 42 deletions
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8
src/main/scala/IF.scala
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@ -23,7 +23,8 @@ class InstructionFetch extends MultiIOModule {
*/
val io = IO(
new Bundle {
val PC = Output(UInt())
val PC = Output(UInt(32.W))
val instruction = Output(new Instruction)
})
val IMEM = Module(new IMEM)
@ -44,12 +45,11 @@ class InstructionFetch extends MultiIOModule {
*/
io.PC := PC
IMEM.io.instructionAddress := PC
// PC := PC + 4.U
PC := PC + 4.U
val instruction = Wire(new Instruction)
instruction := IMEM.io.instruction.asTypeOf(new Instruction)
io.instruction := instruction
/**
* Setup. You should not change this code.