Working adder.

src/main/scala/IDBarrier.scala

@@ -0,0 +1,40 @@
+package FiveStage
+
+import chisel3._
+import chisel3.experimental.MultiIOModule
+
+class IDBarrier extends MultiIOModule {
+  val io = IO(
+    new Bundle {
+      val op1in = Input(SInt(32.W))
+      val op1out = Output(SInt(32.W))
+      val op2in = Input(SInt(32.W))
+      val op2out = Output(SInt(32.W))
+      val ALUopIn = Input(UInt(4.W))
+      val ALUopOut = Output(UInt(4.W))
+      val writeAddrIn = Input(UInt(5.W))
+      val writeAddrOut = Output(UInt(5.W))
+      val writeEnableIn = Input(Bool())
+      val writeEnableOut = Output(Bool())
+    })
+
+  val op1 = RegInit(SInt(32.W), 0.S)
+  op1 := io.op1in
+  io.op1out := op1
+
+  val op2 = RegInit(SInt(32.W), 0.S)
+  op2 := io.op2in
+  io.op2out := op2
+
+  val ALUop = RegInit(UInt(4.W), 0.U)
+  ALUop := io.ALUopIn
+  io.ALUopOut := ALUop
+
+  val writeAddr = RegInit(UInt(5.W), 0.U)
+  writeAddr := io.writeAddrIn
+  io.writeAddrOut := writeAddr
+
+  val writeEnable = RegInit(Bool(), false.B)
+  writeEnable := io.writeEnableIn
+  io.writeEnableOut := writeEnable
+}