Working adder.

src/main/scala/ID.scala

@@ -1,6 +1,6 @@
 package FiveStage
 import chisel3._
-import chisel3.util.{ BitPat, MuxCase }
+import chisel3.util.{BitPat, MuxCase, MuxLookup}
 import chisel3.experimental.MultiIOModule
 
 
@@ -18,32 +18,56 @@ class InstructionDecode extends MultiIOModule {
 
   val io = IO(
     new Bundle {
-      /**
-        * TODO: Your code here.
-        */
+      val instruction = Input(new Instruction)
+      val pc = Input(UInt(32.W))
+      val op1 = Output(SInt(32.W))
+      val op2 = Output(SInt(32.W))
+      val ALUOp = Output(UInt(4.W))
+      val writeAddrIn = Input(UInt(5.W))
+      val writeAddrOut = Output(UInt(5.W))
+      val writeEnableIn = Input(Bool())
+      val writeEnableOut = Output(Bool())
+      val writeData = Input(UInt(32.W))
     }
   )
 
   val registers = Module(new Registers)
   val decoder   = Module(new Decoder).io
 
-
-  /**
-    * Setup. You should not change this code
-    */
   registers.testHarness.setup := testHarness.registerSetup
   testHarness.registerPeek    := registers.io.readData1
   testHarness.testUpdates     := registers.testHarness.testUpdates
 
+  registers.io.readAddress1 := io.instruction.registerRs1
+  registers.io.readAddress2 := io.instruction.registerRs2
+  registers.io.writeEnable  := io.writeEnableIn
+  registers.io.writeAddress := io.writeAddrIn
+  registers.io.writeData    := io.writeData
 
-  /**
-    * TODO: Your code here.
-    */
-  registers.io.readAddress1 := 0.U
-  registers.io.readAddress2 := 0.U
-  registers.io.writeEnable  := false.B
-  registers.io.writeAddress := 0.U
-  registers.io.writeData    := 0.U
+  decoder.instruction := io.instruction
 
-  decoder.instruction := 0.U.asTypeOf(new Instruction)
+  val select1Map = Array(
+    Op1Select.rs1 -> registers.io.readData1.asSInt(),
+    Op1Select.PC -> io.pc.asSInt(),
+  )
+  io.op1 := MuxLookup(decoder.op1Select, 0.S(32.W), select1Map)
+
+  val select2ImmMap = Array(
+    ImmFormat.ITYPE       -> decoder.instruction.immediateIType,
+    ImmFormat.STYPE       -> decoder.instruction.immediateSType,
+    ImmFormat.BTYPE       -> decoder.instruction.immediateBType,
+    ImmFormat.UTYPE       -> decoder.instruction.immediateUType,
+    ImmFormat.JTYPE       -> decoder.instruction.immediateJType,
+    ImmFormat.SHAMT       -> decoder.instruction.immediateZType,
+    ImmFormat.SHORT_ITYPE -> decoder.instruction.immediateShortIType,
+  )
+  val select2Map = Array(
+    Op2Select.imm -> MuxLookup(decoder.immType, 0.S(32.W), select2ImmMap),
+    Op2Select.rs2 -> registers.io.readData2.asSInt(),
+  )
+  io.op2 := MuxLookup(decoder.op2Select, 0.S(32.W), select2Map)
+
+  io.ALUOp := decoder.ALUop
+  io.writeAddrOut := decoder.instruction.registerRd
+  io.writeEnableOut := decoder.controlSignals.regWrite
 }