Working adder.

This commit is contained in:
Sebastian Bugge 2024-09-27 04:22:10 +02:00
parent 88cab777f9
commit 44ccf12cad
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
9 changed files with 214 additions and 42 deletions

View file

@ -0,0 +1,29 @@
package FiveStage
import chisel3._
import chisel3.experimental.MultiIOModule
class EXBarrier extends MultiIOModule {
val io = IO(
new Bundle {
val writeDataIn = Input(UInt(32.W))
val writeDataOut = Output(UInt(32.W))
val writeAddrIn = Input(UInt(5.W))
val writeAddrOut = Output(UInt(5.W))
val writeEnableIn = Input(Bool())
val writeEnableOut = Output(Bool())
})
val writeData = RegInit(UInt(32.W), 0.U)
writeData := io.writeDataIn
io.writeDataOut := writeData
val writeAddr = RegInit(UInt(5.W), 0.U)
writeAddr := io.writeAddrIn
io.writeAddrOut := writeAddr
val writeEnable = RegInit(Bool(), false.B)
writeEnable := io.writeEnableIn
io.writeEnableOut := writeEnable
}