Working adder.

src/main/scala/EX.scala

@@ -0,0 +1,23 @@
+package FiveStage
+import Chisel.MuxLookup
+import chisel3._
+import chisel3.util.{BitPat, MuxCase}
+import chisel3.experimental.MultiIOModule
+
+
+class Execute extends MultiIOModule {
+  val io = IO(
+    new Bundle {
+      val op1 = Input(SInt(32.W))
+      val op2 = Input(SInt(32.W))
+      val ALUOp = Input(UInt(4.W))
+      val ALUResult = Output(SInt(32.W))
+    }
+  )
+
+  val ALUOpsMap = Array (
+    ALUOps.ADD -> (io.op1 + io.op2)
+  )
+
+  io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap)
+}