kaholaz/TDT4255
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Working adder.

Browse source
This commit is contained in:
Sebastian Bugge 2024-09-27 04:22:10 +02:00
parent 88cab777f9
commit 44ccf12cad
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
9 changed files with 214 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

32
src/main/scala/CPU.scala
View file

@ -21,14 +21,14 @@ class CPU extends MultiIOModule {
/**
You need to create the classes for these yourself
*/
// val IFBarrier = Module(new IFBarrier).io
// val IDBarrier = Module(new IDBarrier).io
// val EXBarrier = Module(new EXBarrier).io
val IFBarrier = Module(new IFBarrier).io
val IDBarrier = Module(new IDBarrier).io
val EXBarrier = Module(new EXBarrier).io
// val MEMBarrier = Module(new MEMBarrier).io
val ID = Module(new InstructionDecode)
val IF = Module(new InstructionFetch)
// val EX = Module(new Execute)
val EX = Module(new Execute)
val MEM = Module(new MemoryFetch)
// val WB = Module(new Execute) (You may not need this one?)
@ -54,4 +54,28 @@ class CPU extends MultiIOModule {
/**
TODO: Your code here
*/
IFBarrier.PCin := IF.io.PC
IFBarrier.instructionIn := IF.io.instruction
ID.io.instruction := IFBarrier.instructionOut
ID.io.pc := IFBarrier.PCout
IDBarrier.op1in := ID.io.op1
IDBarrier.op2in := ID.io.op2
IDBarrier.ALUopIn := ID.io.ALUOp
IDBarrier.writeEnableIn := ID.io.writeEnableOut
IDBarrier.writeAddrIn := ID.io.writeAddrOut
EX.io.op1 := IDBarrier.op1out
EX.io.op2 := IDBarrier.op2out
EX.io.ALUOp := IDBarrier.ALUopOut
EXBarrier.writeEnableIn := IDBarrier.writeEnableOut
EXBarrier.writeAddrIn := IDBarrier.writeAddrOut
EXBarrier.writeDataIn := EX.io.ALUResult.asUInt()
ID.io.writeData := EXBarrier.writeDataOut
ID.io.writeEnableIn := EXBarrier.writeEnableOut
ID.io.writeAddrIn := EXBarrier.writeAddrOut
}