Almost working jump.

src/main/scala/CPU.scala

@@ -66,6 +66,8 @@ class CPU extends MultiIOModule {
   IDBarrier.r1ValueIn := ID.io.r1Value
   IDBarrier.r2ValueIn := ID.io.r2Value
   IDBarrier.ALUopIn := ID.io.ALUOp
+  IDBarrier.returnAddrIn := ID.io.returnAddr
+  IDBarrier.jumpIn := ID.io.jump
   IDBarrier.branchTypeIn := ID.io.branchType
   IDBarrier.writeEnableIn := ID.io.writeEnableOut
   IDBarrier.writeAddrIn := ID.io.writeAddrOut
@@ -82,12 +84,16 @@ class CPU extends MultiIOModule {
   EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt()
   EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt()
   EXBarrier.branchIn := EX.io.branch
+  EXBarrier.jumpIn := IDBarrier.jumpOut
+  EXBarrier.returnAddrIn := IDBarrier.returnAddrOut
   EXBarrier.writeEnableIn := IDBarrier.writeEnableOut
   EXBarrier.writeAddrIn := IDBarrier.writeAddrOut
   EXBarrier.memWriteIn := IDBarrier.memWriteOut
   EXBarrier.memReadIn := IDBarrier.memReadOut
 
   MEM.io.ALUResult := EXBarrier.ALUResultOut
+  MEM.io.jump := EXBarrier.jumpOut
+  MEM.io.returnAddr := EXBarrier.returnAddrOut
   MEM.io.writeMem := EXBarrier.memWriteOut
   MEM.io.readMem := EXBarrier.memReadOut
   MEM.io.writeData := EXBarrier.r2ValueOut

src/main/scala/Decoder.scala

@@ -84,6 +84,10 @@ class Decoder() extends Module {
     BGE    -> List(N,        N,       N,        Y,       N,    branchType.gte,  PC,             imm,       ImmFormat.BTYPE,  ALUOps.ADD   ),
     BLTU   -> List(N,        N,       N,        Y,       N,    branchType.ltu,  PC,             imm,       ImmFormat.BTYPE,  ALUOps.ADD   ),
     BGEU   -> List(N,        N,       N,        Y,       N,    branchType.gteu, PC,             imm,       ImmFormat.BTYPE,  ALUOps.ADD   ),
+
+    // signal      regWrite, memRead, memWrite, branch,  jump, branchType,      Op1Select,      Op2Select, ImmSelect,        ALUOp
+    JAL    -> List(Y,        N,       N,        Y,       Y,    branchType.jump, PC,             imm,       ImmFormat.JTYPE,  ALUOps.ADD   ),
+    JALR   -> List(Y,        N,       N,        Y,       Y,    branchType.jump, rs1,            imm,       ImmFormat.JTYPE,  ALUOps.ADDR  ),
   )
 
 

src/main/scala/EX.scala

@@ -31,6 +31,7 @@ class Execute extends MultiIOModule {
     ALUOps.SRA    -> (io.op1 >> io.op2(4, 0)),
     ALUOps.SRL    -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
     ALUOps.SLL    -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
+    ALUOps.ADDR   -> ((io.op1 + io.op2) & -2.S),
     ALUOps.COPY_A -> io.op1,
     ALUOps.COPY_B -> io.op2,
   )

src/main/scala/EXBarrier.scala

@@ -9,6 +9,8 @@ class EXBarrier extends MultiIOModule {
       val ALUResultIn = Input(UInt(32.W))
       val ALUResultOut = Output(UInt(32.W))
       val branchAddress = Output(UInt(32.W))
+      val returnAddrIn = Input(UInt(32.W))
+      val returnAddrOut = Output(UInt(32.W))
       val r2ValueIn = Input(UInt(32.W))
       val r2ValueOut = Output(UInt(32.W))
       val writeAddrIn = Input(UInt(5.W))
@@ -21,6 +23,8 @@ class EXBarrier extends MultiIOModule {
       val memWriteOut = Output(Bool())
       val branchIn = Input(Bool())
       val branchOut = Output(Bool())
+      val jumpIn = Input(Bool())
+      val jumpOut = Output(Bool())
     })
 
   io.ALUResultOut := io.ALUResultIn
@@ -28,6 +32,10 @@ class EXBarrier extends MultiIOModule {
   branchAddress := io.ALUResultIn
   io.branchAddress := branchAddress
 
+  val returnAddr = RegInit(UInt(32.W), 0.U)
+  returnAddr := io.returnAddrIn
+  io.returnAddrOut := returnAddr
+
   val r2Value = RegInit(UInt(32.W), 0.U)
   r2Value := io.r2ValueIn
   io.r2ValueOut := r2Value
@@ -51,5 +59,9 @@ class EXBarrier extends MultiIOModule {
   val branch = RegInit(Bool(), false.B)
   branch := io.branchIn
   io.branchOut := branch
+
+  val jump = RegInit(Bool(), false.B)
+  jump := io.jumpIn
+  io.jumpOut := jump
 }
 

src/main/scala/ID.scala

@@ -33,6 +33,8 @@ class InstructionDecode extends MultiIOModule {
       val memWrite = Output(Bool())
       val memRead = Output(Bool())
       val branchType = Output(UInt(3.W))
+      val jump = Output(Bool())
+      val returnAddr = Output(UInt(32.W))
     }
   )
 
@@ -73,6 +75,9 @@ class InstructionDecode extends MultiIOModule {
   io.r1Value := registers.io.readData1
   io.r2Value := registers.io.readData2
 
+  io.jump := decoder.controlSignals.jump
+  io.returnAddr := io.pc + 4.U
+
   io.ALUOp := decoder.ALUop
   io.branchType := decoder.branchType
   io.writeAddrOut := decoder.instruction.registerRd

src/main/scala/IDBarrier.scala

@@ -14,6 +14,10 @@ class IDBarrier extends MultiIOModule {
       val r1ValueOut = Output(UInt(32.W))
       val r2ValueIn = Input(UInt(32.W))
       val r2ValueOut = Output(UInt(32.W))
+      val returnAddrIn = Input(UInt(32.W))
+      val returnAddrOut = Output(UInt(32.W))
+      val jumpIn = Input(Bool())
+      val jumpOut = Output(Bool())
       val ALUopIn = Input(UInt(4.W))
       val ALUopOut = Output(UInt(4.W))
       val branchTypeIn = Input(UInt(3.W))
@@ -44,6 +48,14 @@ class IDBarrier extends MultiIOModule {
   r2Value := io.r2ValueIn
   io.r2ValueOut := r2Value
 
+  val returnAddr = RegInit(UInt(32.W), 0.U)
+  returnAddr := io.returnAddrIn
+  io.returnAddrOut := returnAddr
+
+  val jump = RegInit(UInt(32.W), 0.U)
+  jump := io.jumpIn
+  io.jumpOut := jump
+
   val ALUop = RegInit(UInt(4.W), 0.U)
   ALUop := io.ALUopIn
   io.ALUopOut := ALUop

src/main/scala/MEM.scala

@@ -23,6 +23,8 @@ class MemoryFetch() extends MultiIOModule {
       val readMem = Input(Bool())
       val writeMem = Input(Bool())
       val dataOut = Output(UInt(32.W))
+      val jump = Input(Bool())
+      val returnAddr = Input(UInt(32.W))
     })
 
 
@@ -49,5 +51,5 @@ class MemoryFetch() extends MultiIOModule {
   DMEM.io.writeEnable := io.writeMem
 
   DMEM.io.dataAddress := Mux(io.writeMem, ALUResult, io.ALUResult)
-  io.dataOut := Mux(io.readMem, DMEM.io.dataOut, ALUResult)
+  io.dataOut := Mux(io.readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, ALUResult))
 }

src/main/scala/ToplevelSignals.scala

@@ -119,6 +119,7 @@ object ALUOps {
   val SRA    = 9.U(4.W)
   val COPY_A = 10.U(4.W)
   val COPY_B = 11.U(4.W)
+  val ADDR   = 12.U(4.W)
 
   val DC     = 15.U(4.W)
 }

src/test/resources/tests/jump.s

@@ -0,0 +1,11 @@
+main:
+    addi x2, x2, 4
+    j loop
+
+end:
+    done
+
+loop:
+    bge x1, x2, end
+    addi x1, x1, 1
+    j loop